SOLTEK SL-65F+ User Manual And Technical Manual page 21

65F+ BIOS
Memory Hole At 15M-
Choose Enabled or Disabled (default). In order to improve
performance, certain space in memory can be reserved for
16M
ISA cards. This memory must be mapped into the memory's
space below 16MB. Enable this option will cause memory
only connect to 16MB.
System BIOS
Choose Enabled or Disabled (default). When Enabled, the
access to the system BIOS ROM addressed at F0000H-
Cacheable
FFFFFH is cached.
Choose Enabled or Disabled (default). When enabled, the
Video BIOS Cacheable
access to the VGA BIOS ROM addressed at C0000H ~
C7FFFH is cached.
Video RAM Cacheable Choose Enabled or Disabled (default). When enabled, the
access to the VGA RAM addressed is cached.
This delay happens when the CPU is running so much faster
8 bit I/O Recovery Time
than the I/O bus that the CPU must be delayed to allow for
the completion of the I/O.
The choice for 8 bit I/O: NA, 1, 2, 3 (default), 4, 5, 6, 7, 8.
This delay happens when the CPU is running so much faster
16 bit I/O Recovery Time
than the I/O bus that the CPU must be delayed to allow for
the completion of the I/O.
The choice for 16 bit I/O: NA, 1, 2 (default), 3, 4.
When enabled, CPU to PCI bus accesses are allowed when
Passive Release
passive release. Otherwise, the arbiter only accepts another
PCI master access to local DRAM.
The choice: Enabled (default), Disabled.
Delay Transaction The chipset has an embedded a 32-bit posted write buffer to
support delay transaction cycles. Select enabled to support
compliance with PCI specification version 2.1.
The choice: Enabled (default), Disabled.
AGP Aperture Size (MB) Choose 4, 8, 16, 32, 64 (default), 128 or 256MB. Memory
map and graphics data structures can reside in a Graphics
Aperture. This area is like a linear buffer. BIOS will automati-
cally report the starting address of this buffer to the O.S.
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