Video Data Output For The A504K/Kc - Basler A500k User Manual

Camera Interface

2.5.5 Video Data Output for the A504k/kc

cameras output the video data in a 10 * 8 Bit data stream.
k
A504
The pixel clock is used to time data sampling and transmission. As shown in Figures
the camera samples and transmits data on each rising edge of the pixel clock.
The image has a maximum size of 1280*1024 pixels that are transmitted with a Pixel Clock
frequency of 67.58MHz over the three Channel Link transmitter/receiver pairs X, Y and Z. With
each clock cycle ten pixels at a depth of 8 Bits are transmitted in parallel. Therefore one line takes
a maximum of 128 clock cycles to become transmitted. For more details about sensor timing,
please refer to the Micron MV13 data sheet (www.micron.com).
Due to the internal sensor design, the Area of Interest feature is restricted in horizontal directions
to values that are multiples of ten. For details please read the register description of the AOI
Starting Column and the AOI Width register. Image is transmitted line by line from top left to
bottom right. Frame Valid (FVAL) and Line Valid (LVAL) mark the beginning and duration of frame
and line.
The line valid bit indicates that a valid line is being transmitted. Pixel data is valid when the line
valid bit is high.
The sensor outputs 10 Bits, but two bits output from each ADC are dropped and only 8 bits of data
per pixel is transmitted. The digital shift function selects the bits to be dropped (see section 3.8).
The data sequence outlined below, along with Figures
happening at the inputs to the Channel Link transmitters in the camera.
Note that the timing used for sampling the data at the Channel Link receivers in the
frame grabber varies from device to device. On some receivers, data must be sam-
pled on the rising edge of the pixel clock (receive clock), and on others, it must be
sampled on the falling edge. Also, some devices are available which allow you to
select either rising edge or falling edge sampling. Please consult the data sheet for
the receiver that you are using for specific timing information.
Video Data Sequence for the A504k/kc
When the camera is not transmitting valid data, the frame valid and line valid bits sent on each
cycle of the pixel clock will be low. The camera can acquire a frame and, at the same time, send
the previous frame. It can also first acquire a frame and then send it. When Frame valid becomes
high, the camera starts to send valid data:
• On the pixel clock cycle where frame data transmission begins, the frame valid bit will
become high. One pixel clock later, the line valid bit will become high (if AOI Starting Column
= 0).
• On the pixel clock cycle where data transmission for line one begins, the line valid bit will
become high. Ten data streams are transmitted in parallel during this clock cycle. The first
pixel is the first pixel in the first data stream D_0. The second pixel is the first pixel in the sec-
ond data stream D_1, and so on. The tenth data stream D_10 contains the tenth pixel. 8 bits
will contain the data for each pixel.
• On the next cycle of the pixel clock, the line valid bit will be high. The eleventh pixel is the
second pixel in the D_0 data stream. The twelfth pixel is the second pixel in the D_1 data
stream, and so on. The tenth D_9 data stream contains the twentieth pixel. 8 bits will contain
the data for each pixel.
• On the next cycle of the pixel clock, the line valid bit will be high. The twenty first pixel is the
third pixel in the D_0 data stream. The twenty second pixel is the third pixel in the D_1 data
2-16
PRELIMINARY
2-7 and 2-8,
2-7 and 2-8, describe what is
Basler A500
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