Mpu And Peripheral Circuits; Reset Circuit (1); Reset Circuit (2); Eeprom - NEC MultiSync LCD2080UX -BKA Service Manual

2.6 MPU and Peripheral Circuits

2.6.1 Reset Circuit (1)

Resetting of the MPU is effected by IC801. The source voltage is raised from zero volt to 3.3Vdc and the
resetting condition of the MPU is canceled after about 34ms after the moment when the potential at IC801
Pin 2 reaches 1.25V. In case of MPU runaway, this MPU can be forcibly reset from the outside, by pressing
POWER and RESET of the front key simultaneously.

2.6.2 Reset Circuit (2)

The reset circuit installed in the periphery of IC802 is used to detect a momentary potential dip of 18V. If
there is any abnormality in the power transformer output or load, IC802 maintains the potential of Pin 6 at
the Low level during the period of about 34ms after the moment when 18V has lowered to about 1.34V.
When the L potential is sensed, the MPU once causes the power transformer output to shift to the PMS
state and then establishes the power again for the panel, the scalar, etc.

2.6.3 EEPROM

The various adjustment data are stored in IC803 that is connected to the MPU through I
from the MPU, the output is generated from Pin 29, but the data input read out of the EEPROM is entered
in Pin 28. The clock signal is used in common for both writing and reading.

2.7 DDC

2.7.1 INPUT1 (IC8A1, IC8A2)

Two banks of EEPROMs, each with a capacity of 8 bits × 128 words, are loaded in this IC. The EDID data
for both digital and analog can be read out of one IC by means of one set of the DDC lines.
The digital/analog changeover is effected by DVI selection of the OSM. The result of selection on the OSM
is written in IC8A2 by the MPU. The output from Pin 5 of IC8A2 is switched over to H or L according to the
written data. The switching of the output H/L status is carried out when this status information is applied to
Pin 11 of the bank changeover terminal in IC8A1. Since IC8A2 is a non-volatile memory that enables the
written data to be held, the required data can be read out by simply feeding a source voltage to IC8A1 and
IC8A2 even though the MPU is not turned on. Please refer 2.7.3

2.7.2 INPUT2 (IC8F1)

This IC has the same characteristics as those of IC8A1. The EDID data for both digital and analog are
written in one IC. However, when the potential at Pin 12 of IC8F1 is lowered to the L level, it becomes
possible to read out the digital data and the analog data independently of each other.
In the same manner as that for IC8A1, data writing in IC8F1 is conducted from one set of the DDC lines.
When the potential at Pin 12 is turned to the H level, only the DDC line on the VGA connector side
becomes available. In the same manner as for IC8A1, two kinds of the EDID data can be written from a set
of the DDC lines under the control from Pin 11 intended for bank changeover. For bank changeover,
similarly as for conventional models, the V sync polarity is discriminated by the MPU and the related setting
is made at IC8A2.

2.7.3 DDC-CI

In the DDC-CI, this unit can be controlled from the host side without using the front key. In the state that a
picture of INPUT1 is displayed, /DVISEL1 of the MPU output terminal is set at L. When /DVISEL1 is set at L,
the sections on Pins 8 and 9 of IC8A1 are turned on and those on Pins 8 and 9 of IC8F1 are turned off
(Hi-Z). In the state that INPUT2 is displayed, /DVISEL1 is set at H, the sections on the IC8A1 side are
turned off and those on the IC8F1 side are turned on. The DDC lines of IC8F1 come in two systems
arranged so that the MPU can always maintain communication with the host DDC line on the picture display
side while the MPU controls the bank changeover Pin 11 according to the display of analog or digital.
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C. For data writing