Scalar (Ic401) And Peripheral Circuits; Internal Block Diagram Of Ic401; Lvds; Clock Generator Circuit - NEC MultiSync LCD2080UX -BKA Service Manual

2.5 Scalar (IC401) and Peripheral Circuits

2.5.1 Internal Block Diagram of IC401

From
IC4A1
No Use
From/To
Flash ROM

2.5.2 LVDS

The 48-bit digital signal output from the scaling IC (IC401) is entered in the LVDS transmitter (IC551,
IC552).
The LVDS signal is transmitted from CN551 to the panel control board, and decoded within this board.

2.5.3 Clock Generator Circuit

Original oscillation is caused in the 14.31818MHz oscillator (X402). Since then, the output is multiplied by 5
times at the PLL (IC403). As a result, a clock signal of 130MHz is gained and fed to IC401. This signal is
called the MCLK and used for the control of SDRAM incorporated in IC401 and also for the internal MPU
system clock (however 1/3) and others.
The difference frequency output is generated from IC403 Pin 4. This output signal is multiplied by 4 times at
another PLL (IC403), and a clock signal of 125MHz is gained and fed to IC401. The multiplied signal is
called the "DCLK" and used for the panel driving clock. However, the panel driving clock is DCLK/2.

2.5.4 Flash Memory

The flash memory (IC402) keeps the program data of the MPU incorporated in IC401. The address bus is
"A[19:1]" and the data bus is "D[15:0]". These program data can be rewritten from CN401 through an
appropriate jig.
Graphics
Input
Port
Video
Input
Port
MPU
TXD / RXD
MCLK
IC804
PW164B-20T
Image
Frame
Scalar
Buffer
General
I/O Port
RESET No Use
7-6
Display
Output
Port
OSD
Controller
DCLK
LVDS
Transmitter