Circuit Block Descriptions; Analog Signal Input Circuit; Analog Signal Processor Circuit (Descriptions Only For G Ch On The Dvi-I Side); Sog Sync Separator Circuit - NEC MultiSync LCD2080UX -BKA Service Manual

2. Circuit Block Descriptions

2.1 Analog Signal Input Circuit

2.1.1 Analog Signal Processor Circuit (Descriptions Only for G ch on the DVI-I Side)

The analog video signal input entered in the DVI-I connector is put in the OP AMP of ICA70A through the
emitter follower circuit of QA70G. This video signal is amplified about twice in this IC. The amplified video
signal is attenuated by RA76A and RA77A to the 1/2 level. Through the C-coupling of CA12, the resultant
signal is entered in the AD converter ICA01.
QA71G and QA72G are the transistors used for the ON/OFF operation of the analog delay circuit. When
they are turned off, DA71G and DA72G and DA73G are turned on and a CR low pass filter is formed by
RA75G, CA73G, CA75G and CA77G. QA81G and QA82G are the transistors used for the ON/OFF
operation of the analog delay circuit. When they are turned off, DA81G and DA82G and DA83G are turned
on and a CR low pass filter is formed by RA85G, CA83G, CA85G and CA87G. Thus a propagation delay
takes place at a high frequency. The amount of delay can be adjusted in 4 steps inclusive of "no
compensation" through the selective changeover of QA71G and QA72G. The high-domain frequency
attenuated in the delay circuit is automatically compensated for by the function of sharpness available in
IC4A1. For the purpose of waveform correction, QA73G and QA83G are used to sharpen the blunt video
signal caused by raising the high-frequency gain.

2.1.2 SOG Sync Separator Circuit

After the completion of C-coupling, the G input signal is amplified to about three times at the current
feedback type OP AMP of ICA70A through the video buffer circuit of QA70G and the SOG buffer circuit of
QAM1 call for a power supply of negative potential.
The 3-times amplified signal is processed at the emitter earthed transistors (QAH1 and QAH2) and only the
sync signal component of about 3.3V in the amplitude is output to the collector. The waveform of this output
is shaped up at the Schmitt input inverter. Since then the output signal is entered in the signal processor
LSI (IC4A1). This signal is used for the frequency measurement of the SOG signal.
At the time of the entry of the SOG signal input, the horizontal sync signal intended for the generation of the
PLL clock for the AD converter is gained from the output of ICA70A and through the potential division by
RA76A/RA77A and RA86A/RA87A. The obtained output is entered in the AD converter of ICA01. In the
inside of AD, there is a comparator intended for the separation of video signals from sync signals. The slice
level can be adjusted with the use of the advanced menu.

2.1.3 Sync Signal Changeover Circuit

1) Sync signal for measurements (separate, composite)
The horizontal (or composite) sync signal input entered in the Schmidt inverter of ICAA1 is entered
together with the vertical sync signals in the signal processor IC (IC4A1) through the waveform shaping
Schmidt inverter of IC4A2 and IC4A3.
2) Sync signals for AD sampling clock
The horizontal (or composite) sync signal input entered in the Schmidt inverter of ICAA1 and ICAA2 is
entered in the AD converter (ICA01) through the analog switch of ICAA3 and ICAA4. The horizontal
signal input entered in the AD converter is used as a PLL phase comparator signal intended for the
generation of AD sampling clock signals. ICAA3 and ICAA4 has a function of sync signal line ON-OFF so
that "signals are transmitted at a low resistance in normal operation and the AD converter is protected in
the PMS mode."
3) Sync signals for measurements (SOG)
The SOG sync signal input of 3.3V in the amplitude, entered in the Schmidt inverter of ICAA1 and ICAA2,
is entered in the signal processor IC (IC4A1) through ICAA6. This ICAA6 has a function of separation
sync signal changeover so that "a high separation performance characteristic is gained in ordinary
operation and less power is consumed in the PMS mode."
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