Ad Converter; Digital Signal Input Block; Ic4A1 Signal Processor Block - NEC MultiSync LCD2080UX -BKA Service Manual

4) Schmidt power supply changeover circuit
The source voltage of the Schmidt inverter consisting of ICAA1 and ICAA2 is controlled by changing over
the feedback voltage of ICAA6 with the aid of the SMT 2.7V signal that has been controlled by the MPU.
When the sync waveform becomes blunt and a step-state waveform is observed in the vicinity of the
threshold level of the Schmidt inverter (FINE noise does not disappear in the picture), the source voltage
is changed with the advanced menu to regulate the threshold voltage.

2.2 AD Converter

Changeover of the two signals is controlled inside the AD converter, and this control is effected from the
2
MPU through the I C bus.
The AD converter (ICA01) is used to convert the RGB video signals of about 0.7Vp-p into the digital signals
of 8 bits each, 24 bits in total. The conversion clock into the digital signals is based on the horizontal sync
signal. The clock signal is generated in ICA01 by the incorporated PLL circuit.
The video signal input is entered in ICA01 through the C-coupling by CA05 to CA10. This signal input is
clamped at the input stage of ICA01 by the clamp pulses in the horizontal back porch block. The clamp
pulses are generated from the previously mentioned horizontal signals in the signal processor IC (ICA01),
and entered in Pin 30. After clamping, the video signals pass through the built-in pre-AMP and AD
conversion is effected with the sampling clock generated by the above-mentioned PLL.
The register used to set up the clamp pulses and the pre-AMP gain is controlled through the I
31 to 21. The circuit components of CA21, CA2A, CA22, and RA30 connected to Pin 50 are used to
establish a loop filter for the generation of the PLL clock. If this block involves any abnormality, pictures
cannot be reproduced correctly.
SOG and COMPOSITE SYNC are used to suspend the PLL phase comparison during the vertical blanking
by the COAST (or called HOLD) generated in the inside of ICA01. If this signal is not available, the clock
frequency changes during the vertical period and a curve is produced in the upper part of the screen.

2.3 Digital Signal Input Block

The TMDS (panel link) signal is decoded by the receiver IC circuit (ICK01, ICK02) and then converted into a
digital signal of 48 bits. (The digital signal is used to select the Input 1 or Input 2 side while a wired OR
circuit is established by the outputs of ICK01 and ICK02 and the PDO terminal of ICK01 and ICK02 is
controlled by the MPU (IC804).)

2.4 IC4A1 Signal Processor Block

When the output image data are received from the ADC (ICA01) or the TMDS receiver (ICK01, ICK02) and
the processing described below is carried out in the inside of IC4A1, the image data are sent out to the
scalar of IC401.
1) Detection, measurement, and discrimination of sync signals
2) Input signal position control (RGB individual control enabled)
3) ADC/TMDS* input signal changeover
4) Color adjustment
* Mutual TMDS changeover is effected through the control of the PD/PDO terminal by the MPU.
7-5
2
C bus of Pins