Daq Signal Timing; Scanclk Signal - Measurement Computing PCI-DAS6013 User Manual

Analog and digital i/o board
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PCI-DAS6013 and PCI-DAS6014 User's Guide

DAQ signal timing

The DAQ timing signals are:
SCANCLK
A/D START TRIGGER
A/D STOP TRIGGER
STARTSCAN
SSH
A/D CONVERT
A/D PACER GATE
A/D EXTERNAL TIMEBASE
A/D STOP

SCANCLK signal

SCANCLK is an output signal that may be used for switching external multiplexers. It is
a 400 ns wide pulse that follows the CONVERT signal after a 50 ns delay. This is
adequate time for the analog input signal to be acquired so that the next signal may be
switched in. The polarity of the SCANCLK signal is programmable. The default output
pin for the SCANCLK signal is AUXOUT2, but any of the AUXOUT pins may be
programmed as a SCANCLK output.
CONVERT
SCANCLK
Figure 4-2. SCANCLK Signal Timing
t
t
d
d
t
= 50 ns
d
4-4
Functional Details
t
w
t
= 400 ns
w

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