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iSBC 80/30
AS9-6, A42-6, and A41-8 (8ZB4) decides which func-
tion (transmit or receive) to select for the Data Bus Driver.
This decision is based on the mode (master or slave) that
the board is in and whether the command is a read or a
write. For the master mode, a Write Command selects the
transmit function (DIEN is driven high); a Read Com-
mand selects the receive function (DIEN is driven low).
The BUS Controller examines its 10RR, 10WR, MRDR,
and MWTR inputs and drives the appropriate command
line low on the Multibus. After the command is acknowl-
edged (signified by the addressed device driving AACK/
or XACK/ low), the CPU terminates the appropriate
command and tristates its address lines. This deselects the
Address Bus Drivers and Data Bus Drivers and causes
QCMD/ to go false (high). The Bus Controller relin-
quishes control of the Multibus by driving BREQ/ high
and BPRO/ low and then raising BUSY/.
It should be noted that, after gaining control of the Mul-
tibus, the iSBC 80/30 can invoke an override condition to
prevent losing control at a critical time. (For instance, it
may be desired to execute several consecutive commands
without having to contend for the bus after each command
is executed.) Bus override is invoked by executing a SIM
instruction with accumulator bits 6 and 7
=
1, which
causes the CPU SOD line to drive the Bus Controller
OVRD input high.
4-35. I/O OPERATION
The following paragraphs describe on-board and system
I/O operations. The actual functions performed by
specific read and write commands to on -board I/O devices
are described in Chapter 3.
4-36.
ON-BOARD I/O OPERATION.
Address bits
AB2-AB7 are applied to I/O Address Decoder ASO and
associated input chip enable gates (6Z7 A). Address bits
AB4-AB7 are decoded by A48-12, A6S-6, and A6S-3
to provide El, E2, and E3 enable inputs to ASO; when
enabled, ASO decodes address bits AB2-AB4 toprovide
chip select inputs to the appropriate I/O device. Address
bits AB2-AB7 are decoded as follows:
Bits
Chip Select
Addresses
7 6 5 4 3 2
Signal
1 1
o
1 1 0
08-0B
8259CS/
1 1
o
1 1 1
~C-OF
8253CS/
1 1 100 1
E4-E7
8741CS/
1 1 101 0
E8-EB
8255CS/
1 1 1 0 1 1
EC-EF
8251CS/
When anyone of the five outputs of ASO goes low, the I/O
ADR signal from the CPU (buffered 10/M) is driven
through A46-11 to develop I/O AACK/. The I/O AACK!
signal drives the CPU READY line high and, together
Principles of Operation
with the COMMAND/ signal (decoded WR or RD),
enables Data Buffer A24 (4ZC6). The function of A24 is
selected by the CPU S 1 output; S 1
=
1 for read operations
and S 1
=
0 for write operations. For example, data is
transferred from the DIOO-DI07 lines to the DBO-DB7
lines when SI
=
1.
After the I/O device has been selected by address bits
AB2-AB7, specific functions for the chip are selected by
address bits ABO-AB!. (Refer to table 3-2.)
4-37.
SYSTEM I/O OPERATION.
Address bits
AB2-AB7 are decoded by I/O Address Decoder ASO as
described in paragraph 4-31. If the address is not for an
on-board I/O device, I/O AACK/ remains false (high)
and, together with QCMD/, activates the Bus Controller
XSTR input. The false SLAVE MODE/ signal from
ASS-9 (9ZC4) in the Dual Port Control logic enables
Address Buffer AS3/ AS4 and, together with the false I/O
AACK/ signal, enables Data Buffer A52.
When the B us Controller gains control of the Multibus as
described in paragraph 4-29, it drives ADEN/ low to
select Address Bus Driver A72/A73 and Data Bus Driver
A74/A7S. Since the board is not in the slave mode, the
QSLA VE RQT/ signal is false (high) and the Address Bus
Driver transmit function is selected. The transmit or re-
ceive function of Data Buffer is selected by the CPU SI
line. If the operation is a read, S 1
=
1 and the receive
function is enabled; for a write, SI
=
0 and the transmit
function is enabled. The steering logic composed of
A39-6, AS8-6, A42-6, and A41-8 (8ZB4) decides which
function to select for the Data Bus Driver. Since the board
is in the master mode for off-board operations, a write
operation selects the transmit function and a read opera-
tion selects the receive function.
After gaining control of the Multibus the B us Controller
proceeds with the control tasks for the remainder of the
I/O transfer. Refer to paragraph 4-29 for a description of
how the Bus Controller terminates bus control.
4-38. ROM/EPROM OPERATION
The two ROM/EPROM chips are installed by the user in
IC sockets A2S/ A37 (3ZA3). Memory addresses 0000-
IFFF are reserved exclusively for ROM/EPROM; the
actual occupied memory space depends on the ROM/
EPROM chips as follows:
Chip
Chip Addresses In
Size
A25
A3
1K
x
8
0OOO-03FF
0400-07FF
2K
x
8
0OOO-07FF
0800-0FFF
4K
x
8
OOOO-OFFF
1000-1FFF
Address bits ABO-ABB are applied directly to the inputs
of A2S-A37 and address bits ABA-ABF are applied to the
4-13
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