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General Information
several words to or from on-board RAM, their operations
are interleaved. The slave RAM decode logic allows ex-
tended Multibus addressing so that bus masters having a
20-bit address capability can partition the iSBC 80/30
RAM into any 8K or 16K segment in a I-megabyte
address space. The CPU, however, has only 16 address
lines and memory must therefore reside in the 0-65K byte
address space. There is no conflict in assigning RAM
addresses for CPU access and slave access since separate
decoding logic is used.
Jumpers are included to allow the user to reserve 8K
bytes of on-board RAM for use by the 8085A CPU only.
This reserved RAM address space is not accessible via the
Multibus and does not occupy any system address space.
Two IC sockets are included to accommodate up to .8K of
user-installed ROM or EPROM. Configuration jumpers
allow ROM or EPROM to be installed in lK, 2K, or 4K
increments. All on-board ROM/EPROM operations are
performed at maximum processor speed.
The iSBC 80/30 includes 24 programmable parallel I/O
lines implemented by means of an Intel 8255A Program-
mable Peripheral Interface (PPI). The system software is
used to configure the I/O lines in any combination of
unidirectional input/output and bidirectional ports. The
I/O interface may be customized to meet specific periph-
eral requirements and, in order to take full advantage
of the large number of possible I/O configurations, IC
sockets are provided for interchangeable I/O line drivers
and terminators. Hence, the flexibility of the parallel
I/O interface is further enhanced by the capability of
selecting the appropriate combination of optional line
drivers and terminators to provide the required sink
current, polarity, and drive/termination characteristi9s
for each application. The 24 programmable I/O lines and
signal ground lines are brought out to a 50-pin edge
connector (11) that mates with flat, woven, or round
cable.
Sockets are provided fora user-supplied Inte18041/8741A
Universal Programmable Interface (UPI) and associated
line drivers and terminators. The 8041/8741A is a single-
chip microcomputer which contains a CPU, ) K bytes of
ROM (8041) or EPROM (8741),64 bytes of RAM, 16
programmable I/O lines, and an 8-bit timer. Special inter-
face registers are included in the chip which enable the
UPI to function as a slave processor to the 8085A CPU.
The UPI allows the user to specify algorithms for con-
trolling user peripherals directly in the chip, thereby
relieving the 8085A CPU for other system functions. An
RS232C driver and an RS232C receiver are included so
that the UPI may optionally be used to handle a simple
serial I/O interface. In addiiion to providing the capability
of user-supplied algorithms for the 8041/8741A the
iSBC 80/30 supports all the preprogrammed 8041/8741A
devices such as the Intel 8278 Keyboard Encoder, 8294
Data Encryption Controller, and 8295 Matrix Printer
Driver.
1-2
iSBC 80/30
The RS232C compatible serial I/O port is controlled and
interfaced by an Intel 8251A US ART (Universal Syn-
chronous/Asynchronous Receiver/Transmitter) chip. The
USART is individually programmable for operation in
most synchronous or asynchronous serial data transmission
formats (including IBM Bi-Sync).
In the synchronous mode the following are programmable:
a.
Character length,
b.
Sync character (or characters), and
c.
Parity.
In the asynchronous mode the following are programmable:
a.
Character length,
b.
Baud rate factor (clock divide ratios of 1, 16, or 64).
c.
Stop bits, and
d .. Parity.
In both the synchronous and asynchronous modes, the
serial I/O port features half- or full-duplex, double-buffered
transmit and receive capability. In addition, USART error
detection circuits can check for parity, overrun, and fram-
ing errors. The USART transmit and receive clock rates are
supplied by a programmable baud rate/time generator.
These clocks may optionally be supplied from an external
source. The RS232C command lines, serial data lines, and
signal ground lines are brought. out to a 50-pin edge
connector (13) that mates with flat or round cable.
Three independent, fully programmable 16-bit interval
timer/event counters are provided by an Intel 8253
Programmable Interval Timer (PIT). Each counter is
capable of operating in either BCD or binary modes; two
of these counters are available to the systems designer to
generate accurate time intervals under software control.
Routing for the outputs and gate/trigger inputs of two of
these counters is jumper-selectable; the outputs of these
two counters may be independently routed to the 8259A
Programmable Interrupt Controller (PIC), the I/O line
drivers associated with the 8255A Programmable Periph-
eral Interface (PPI), the 8041/8741A Universal Program-
mable Interface, or used as inputs to the 8255A PPI
and 8041/8741A (UPI). The gate/trigger inputs ofthe two
counters may be routed to I/O terminators associated with
the 8255A PPI or as output connections from the 8255A
PPI. The third counter is used as a programmable baud
rate generator for the serial I/O port. In utilizing the iSBC
80/30, the systems designer simply configures, via
software, each counter independently to meet system
requirements. Whenever a given time delay or count is
needed, software commands to ·the 8253 PIT select the
desired function. The contents of each counter may be
read at any time during system operation with simple
operations for event counting applications, and special
commands are included so that the contents of each
counter can be read "on the fly."
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