Multibus Configuration; Signal Characteristics - Intel iSBC 80 Hardware Reference Manual

iSBC 80/30 Preparation for Use
Table 2-11. 8.255A Port Configuration Jumpers (Continued)
Jumper Configuration
Driver (D)/
Port Mode
Terminator (T) Delete Add Effect Port
Restrictions
E9 1 Output T:A3
*25-26 *23-24
Connects OBFs/ output EB None.
(latched) D: A4,AS,A6 J1-22.
EA Port EA bits perform the
following:
*19-20
10-20 Connects J1-32 to • Bit 0 - Port E9 Interrupt
and
ACKs/ input.
(SSPBI) to interrupt
*9-10
jumper matrix.
• Bit 1 - Port E9 Output
Buffer Full (OBF/) output.
• Bit 2 - Port E9 Acknowl-
edge (ACKI) input.
• Bit 3 - If Port EB is in
Mode 0, bit 3 can be input
or output. Otherwise, bit 3
is reserved.
• Bits 4,5 - Input or output
(both must be in same
direction).
• Bits 6,7 - Depends on
Port EB mode.
EA
o
Input
T:A3 None *21-22 Connects bit 4 to J 1-26.
EB Port EB must be in Mode 0
(upper)
*17-1B Connects bit S to J 1-2B.
for all four bits to be available.
*13-14 Connects bit 6 to J 1-30.
*9-10 Connects bit 7 to J 1-32.
E9 Port E9 must be in Mode 0
for all four bits to be available.
EA
o
Input
T:A4 None *2S-26 Connects bit 0 to J 1-24.
EB Port EB must be in Mode 0
(lower)
*23-24 Connects bit 1 to J 1-22.
for all four bits to be available.
*19-20 Connects bit 2 to J1-20.
*1S-16
Connects bit 3 to J 1-1B. E9
Port E9 must be in Mode 0
for all four bits to be available.
EA
o
Output D: A3 None Same as for Port EA (upper)
EAB Same as for Port EA (upper)
(upper)
(latched) Mode 0 Input.
Mode 0 Input.
EA
o
Output D:A4 None Same as for Port EA (lower)
E9 Same as for Port EA {lower}
(lower)
(latched) Mode 0 Input.
*Default jumper connected at the factory.
2-24. MUL TIBUS CONFIGURATION
For systems applications, the iSBC 80/30 is designed for
installation in a standard Intel iSBC 604/614 Modular
Backplane and Cardcage. (Refer to table 2-1 items 1 and
2.) Alternatively, the iSBC 80/30 can be interfaced to a
user-designed system backplane by means of an 86-pin
connector. (Refer to table 2 -1 item 3.) Multibus signal
characteristics and methods of implementing a serial or
parallel priority resolution scheme for resolving bus
contention in a mUltiple bus master system are described
in the following paragraphs.
..
Always tum off the system power supply before
installing the board in or removing the board
Mode 0 Input.
from the backplane. Failure to observe this pre-
caution can cause damage to' the board.
2-25. SIGNAL CHARACTERISTICS
As shown in figure 1-1, connector PI interfaces the iSBC
80/30 to the Multibus. Connector PI pin assignments are
listed in table 2 -12 and descriptions' of the signal functions
are provided in table 2-13.
The dc characteristics of theiSBC 80/30 bus interface
signals are provided in table 2-14. The ac chara<;ter-
istics of the iSBC 80/30 when operating in the master
mode and slave mode are provided in tables 2-15 and
2-16, respectively. Bus exchange timing diagrams are
provided in figures 2-3 and 2-4.
2-15