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Programming Information
tion, and that the RAM address space depends on whether
the board jumpers are configured to allow the CPU to
access 8K or 16K of on-board RAM.
For Multibus access, the on-board RAM may be mapped
into any 8K or 16K segment within the addressing con-
straints of the controlling bus master. In other words, for
16-bit Multibus addressing, the RAM may be mapped
into any 8K or 16K segment of the 64K byte address
space. For 20-bit Multibus addressing, the RAM· may be
mapped into any 8K or 16K segment of the I-megabyte
address space. Additional information is provided in
paragraphs 2-17 through 2-19.
When the CPU is addressing on-board memory (ROM/
PROM or RAM), an internal PROM or RAM Advanced
Acknowledge (AACK/) is automatically generated to
prevent imposing a CPU wait state. When the CPU is
addressing system
memory
via the Multibus, the CPU
must first gain control of the Multibus and, after the
Memory Read or Memory Write Command is given, must
wait for a Transfer Acknowledge (XACK/) to be received
from the addressed memory device. The Failsafe Timer,
if enabled, will prevent a CPU hang-up in the event of a
memory device equipment failure or a bus failure.
It
should be noted in table 3 -1 that it is possible to
configur~ ROM/PROM such as to create
illegal ad-
dresses. If an illegal address is used in conjunction with a
Memory Write Command to ROM/PROM, a PROM
AACK/ signal is generated as though the address was
legal and the CPU will continue executing the program.
However, in this case, erroneous data will be returned.
3-4. I/O ADDRESSING
The on-board 8085A microprocessor (CPU) communi-
cates with the programmable chips through a sequence of
I/O Read and I/O Write Commands. As shown in table
3 -2, each of these chips recognizes four separate hexadec-
imal I/O addresses that are used to control the various
programmable functions. Where two hexadecimal ad-
dresses are listed for a single function, either address may
be used. For example, an I/O Read Command to ED or EF
will read the status of the 8251A USART.
NOTE
The on-board I/O functions are not accessible to
another bus master via the Multibus.
3-5. SYSTEM INITIALIZATION
When power is initially applied to the system, an Initialize
(INIT/) signal is automatically generated that clears the
internal Program Counter, Instruction Register, and Inter-
rupt Enable flip-flop and '·'resets" the 8251A USART,
8255A PPI, and optional 8041/8741A UPI as follows:
3-2
iSBC 80/30
Table 3-2.
1/0
Address Assignments
1/0
Chip
Address
Select
Function
D80r DA
Write: ICW1, OCW2, and OCW3
Read: Status and Poll
8259A PIC
D9 or DB
Write: ICW2 and OCW1 (Mask)
Read: OCW1 (Mask)
DC
Write: CounterO (Load Count
+
N)
Read: Counter
0
DD
Write: Counter 1 (Load Count
+
N)
Read: Counter 1
8253 PIT
DE
Write:Counter2 (Load Count
+
N)
Read: Counter 2
DF
Write: Control
Read: None
Write: Data
)
Ports 1 and 2
(J2)
are selected by
E4 or E6
8041/8741
•
8041/8741 A
Read: Data
software
UPI
(J2)
instructions.
E5 or E7
Write: Command
Read: Status
E8
Write: Port A (J1)
Read: Port A (J1)
E9
Write: Port B (J1)
Read: Port B (J1)
8255A PPI
EA
Write: Port C (J1)
Read: Port C (J1)
EB
Write: Control
Read: None
EC or EE
Write: Data (J3)
8251A
Read: Data (J3)
USART
Write: Mode or Command
ED or EF
Read: Status
a.
The 8251A USARTis setto an "idle" mode, waiting
for a set of Command Words to program the desired
function.
b.
All three ports of the 8255A PPI are set to the input
mode.
c.
The 8041/8741A UPI internal Program Counter and
Status flip-flops are cleared.
The 8253 PIT and 8259A PIC are not affected by the
power-up sequence.
The INIT/ signal is also gated onto the Multibus to set the
remainder of the system components to a known internal
state.
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