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Summary of Contents for Intel IQ80315
- Page 1 ® Intel IQ80315 I/O Processor Evaluation Platform Board Manual August 2004 Order Number: 253794-003US...
- Page 2 Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Intel may make changes to specifications and product descriptions at any time, without notice.
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Page 3: Table Of Contents
2.12.1 PCI-X Connectors ....................28 2.12.2 DDR SDRAM Connectors..................28 2.12.3 ATX Power Connector ................... 28 2.12.4 Lithium CR2032 Battery Coin Cell Socket ............. 28 2.12.5 DDR SDRAM Backup Battery Pack Holder and Connector........29 ® Intel IQ80315 I/O Processor Evaluation Platform Board Manual... - Page 4 4.2.9.7 Battery Status Register ................47 4.2.10 Diagnostics ......................48 Operating System Support ....................49 Debug Software ........................50 Design Specifications ......................51 Getting Started and Using the Debugger ..............52 ® Intel IQ80315 I/O Processor Evaluation Platform Board Manual...
- Page 5 Hardware Breakpoints ................66 B.9.3 Exception Trapping ....................67 Figures ® Intel IQ80315 Customer Reference Board Functional Block Diagram ........12 ® Intel IQ80315 Customer Reference Board Layout Diagram ............. 13 C Local Serial Bus........................21 DDR I C Serial Bus ........................24 ATX Rear Gasket Dimensions....................
- Page 6 13 LCD and Backlight Connector Pinout ..................33 14 Serial ATA Drive Activity LED Header ..................33 ® 15 Intel IQ80315 Customer Reference Board Hardware Setup Flow Chart........54 16 Software Flow Diagram ......................55 Tables Terms and Definitions........................9 Feature Summary ........................
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Page 7: Intel ® Iq80315 I/O Processor Evaluation Platform Board Manual
Minor corrections to Figure 1, “Intel IQ80315 Customer Reference Board Functional Block August 2004 Diagram” on page August 2004 Added Appendix B, “Getting Started and Using the Debugger.” September 2003 Initial document. ® Intel IQ80315 I/O Processor Evaluation Platform Board Manual... - Page 8 Contents THIS PAGE INTENTIONALLY LEFT BLANK ® Intel IQ80315 I/O Processor Evaluation Platform Board Manual...
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Page 9: Introduction
CRB. Intended Audience ® This board manual is intended to provide detailed technical information about the Intel IQ80315 Customer Reference Board (hereafter “IQ80315 CRB” or “IQ80315”) to software developers, validation engineers, and other engineers and technicians who need this level of information. -
Page 10: Hardware
Intel IQ80315 I/O Processor Evaluation Platform Hardware Overview 2.1.1 Feature Summary Table 2 summarizes the major features of the IQ80315 CRB. Table 2. Feature Summary (Sheet 1 of 2) Feature Details Form Factor Micro ATX—9.60 inches by 9.60 inches ®... - Page 11 • Composite hard-drive activity LED (green) • Header for external hard-drive activity LEDs • Header for a two-line, 40-character LCD display. Audible Alarm PCB mounted buzzer and connector for chassis mounted speaker ® Intel IQ80315 I/O Processor Evaluation Platform Board Manual...
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Page 12: Block Diagram
® Intel IQ80315 I/O Processor Evaluation Platform 2.1.2 Block Diagram Figure 1 is a block diagram of the major functional areas of the IQ80315 CRB. ® Figure 1. Intel IQ80315 Customer Reference Board Functional Block Diagram P I-X Bus1 64Bit - 33/66/100 MHz... -
Page 13: Layout Diagram
PCI-X Connector: 32/64 bits at 66/100 MHz CR2 0 3 2 Lithium Power Reset attery attery Conn Reset tn AA (x 4) attery Pack * Other names and brands may be claimed as property of others. 3446-01 ® Intel IQ80315 I/O Processor Evaluation Platform Board Manual... -
Page 14: Processor
® ® The IQ80315 CRB has two Intel 80200 processors with Intel XScale microarchitecture. The key characteristics of the 80200 processor implementation on the IQ80315 CRB are as follows. • 32-bit address, 64-bit data busses • Core speed: 333–733 MHz •... -
Page 15: Pci-X Subsystem
The IQ80315 CRB has two independent PCI-X busses. Both busses have 64-bit data paths, can run ® at 33, 66 or 100 MHz, and can support either PCI or PCI-X cards. PCI-X bus 1 has two Intel 31244 Serial ATA controllers and one PCI-X slot. PCI-X bus 2 has two PCI-X slots. -
Page 16: Gigabit Ethernet
The Intel 80314 I/O processor companion chip has two integrated 10/100/1000 Mbit/sec Ethernet MAC controllers. The IQ80315 CRB uses a Marvell* 88E1020 transceiver chip to implement the Ethernet physical interface. Shorting the 88E1020 Config[4:0] inputs to V , GND, or one of the LED outputs configures the following options at reset: •... -
Page 17: Peripheral Bus
The Intel 80314 I/O processor companion chip supports an asynchronous general-purpose peripheral bus for devices such as flash, ROM, or SRAM memory. The IQ80315 CRB runs the internal peripheral interface clock at the 80314 core clock frequency. The CPLD buffers the peripheral bus data bus and demultiplexes the address bus. The CompactFlash* and expansion header have 16-bit data busses and are accessed on the PBI_AD[31:16] lines. -
Page 18: Flash
® Eight MB of flash memory is implemented in the IQ80315 CRB using an Intel StrataFlash device. The flash chip is packaged in a 64-ball easy BGA package. The IQ80315 CRB makes the following signal connections to the flash chip: ®... -
Page 19: Compactflash
2.7.3 CompactFlash* The IQ80315 CRB supports a 3.3 V, 16-bit CompactFlash* type II socket on the peripheral bus. The CompactFlash interface is compliant with the CF+ v1.4 CompactFlash specification. The CompactFlash interface of the IQ80315 CRB supports memory and I/O accesses. CompactFlash ATA cards are not supported. -
Page 20: Uart
Intel IQ80315 I/O Processor Evaluation Platform UART The IQ80315 CRB has two 9-pin D-shell serial port connectors mounted on the back panel. These ® are driven by a Max3232E* 3.3 V dual serial port transceiver. The Intel 80314 I/O processor companion chip TX, RX, CTS#, and RTS# signals for each UART are connected to the serial port transceiver. -
Page 21: Main I C Bus Subsystem
Main I C Bus Subsystem The main I C bus is primarily used for miscellaneous storage and support functions. The IQ80315 CRB uses the main I C bus for serial EEPROM, real-time clock, temperature sensors, and fan controllers, while operating at 400 KHz. -
Page 22: Real Time Clock-St Microelectronics* M41St84W
RTC. The square-wave output is buffered and directed to either the buzzer or speaker output by a 3-pin jumper. The IQ80315 CRB supports both a speaker and a buzzer for design flexibility. The buzzer is useful when the board is used without an ATX chassis and the speaker when used with a chassis. -
Page 23: Temperature Sensors-Dual National* Ti-101S
Temperature monitoring is achieved using two National* TI-101 temperature sensors. These are 3.3 V, I C sensors with addresses 0x48 and 0x49. Accuracy is nominally ± 2 °C in the IQ80315 CRBs operating range. The TI-101s are placed on opposite ends of the board, just in case there is a strong temperature gradient present. -
Page 24: Ddr I
EEPROMs have been configured, writing to 0x30, 0x31, or 0x32 write-protects the first 128 bytes of each EEPROM. The IQ80315 CRB operates the DDR SDRAM I C bus at 100 KHz because some SDRAM modules cannot communicate on the I C bus at 400 KHz. -
Page 25: Connectors
2.11.1 Rear Gasket Most of the I/O connectors requiring user access are located in the rear gasket area. The IQ80315 CRB rear gasket area conforms to the standard ATX rear gasket dimensions and location. Figure 5... -
Page 26: Dual Vertical Stack Right Angle 9-Pin D Serial Port Connector
The JTAG Header is a 20-pin, right-angle, shrouded connector. Section 2.11.4 shows the JTAG connector pinout. Table 9. XS JTAG–J4A1 Signal Signal Vref Vsupply NTRST NC (RTCK) NSRST NC (DBGRQ) NC (DBGACK) ® Intel IQ80315 I/O Processor Evaluation Platform Board Manual... -
Page 27: Compactflash* Ii Connector And Eject Mechanism
CFII_INPAK_N CFII_A01 CFII_REG_N CFII_A00 BVD2_N CFII_D00 BVD1_N CFII_D01 CFII_D08 CFII_D02 CFII_D09 CFII_WP_IO_N CFII_D10 CD2_N 2.11.6 Hex Right-Angle Rotary Switch The rotary switch is an NKK DR FC 16 right-angle hex switch. ® Intel IQ80315 I/O Processor Evaluation Platform Board Manual... -
Page 28: Internal Connectors
The DDR SDRAM module connectors are 184-pin AMP* #390241-1 connectors. These are 2.5 V ® keyed connectors. The connector furthest from the Intel 80314 I/O processor companion chip is a different color from the other two DDR SDRAM module connectors in order to help identify where to plug in a single module. -
Page 29: Ddr Sdram Backup Battery Pack Holder And Connector
2.12.6 Fan Connectors for Front and Rear Case The fan connectors are PC standard 3-pin keyed connectors. Figure 9 shows the fan controller pinout. Figure 9. Fan Controller Pinout +FAN-V FB/GND ® Intel IQ80315 I/O Processor Evaluation Platform Board Manual... -
Page 30: Serial-Ata (Sata) Connectors
The unused GPIO and interrupt header is a 0.1", 2 × 14 header. The header pinout is TBD. 2.12.9 Peripheral Bus Test and User Expansion Connector The peripheral bus test/expansion header is a PC104 like 0.1" header. ® Intel IQ80315 I/O Processor Evaluation Platform Board Manual... -
Page 31: I 2 C Headers
® Intel IQ80315 I/O Processor Evaluation Platform 2.12.10 C Headers The I C tests headers are keyed 4-pin headers. Figure 11 shows the I C header pinout. Figure 11. C Header ® Intel IQ80315 I/O Processor Evaluation Platform Board Manual... -
Page 32: Front Panel Connectors
Front Panel Connectors 2.13.1 ATX Front Panel Connector The IQ80315 CRB has a standard ATX 20-pin front panel connector for access to a speaker, reset switch, Power LED, HDD LED, and system power button. Figure 12 shows the ATX front panel header pinout. -
Page 33: S-Ata Drive Activity Led Header
Serial ATA Drive Activity LED Header 3.3V HD LED 0 HD LED 1 HD LED 2 HD LED 3 HD LED 4 HD LED 5 HD LED 6 HD LED 7 ® Intel IQ80315 I/O Processor Evaluation Platform Board Manual... -
Page 34: Switches, Jumpers, And Reset Configuration Strapping
IQ80315 CRB. Configuration signals are pulled low when the switch is on, the jumper is shorted or in the 1–2 position, or a pull-down (Pd) resistor is installed (bold indicates the default setting). - Page 35 On: PCI-X 66 MHz max (default) switch 2 S6B1 Force PCI mode On: PCI mode only (default) switch 3 S6B1 Force 33MHz PCI mode On: 33 MHz PCI mode only (default) switch 4 ® Intel IQ80315 I/O Processor Evaluation Platform Board Manual...
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Page 36: Fixed Reset Configuration Inputs
CPLD Reset Configuration Outputs Signal Reset Option Selected XS_C_IRQ[0] / PWRUP_FADJ 100 MHz CPU bus clock XS_C_IRQ[1] / ® Don’t bypass Intel XScale PWRUP_XS_BYP XS_C_FIQ[1] / Don’t bypass SDRAM PLL PWRUP_SD_BYP ® Intel IQ80315 I/O Processor Evaluation Platform Board Manual... -
Page 37: Miscellaneous Buttons, Switches, And Jumpers
IQ80315 I/O Processor Evaluation Platform 2.14.2 Miscellaneous Buttons, Switches, and Jumpers In addition to the reset configuration options, the IQ80315 CRB contains the following miscellaneous switches and jumpers: • Reset Switch—A momentary, normally open miniature push-button switch is mounted on the motherboard. -
Page 38: Debug Features
LEDs, and several ground points around the board to assist with system debug. Most interfaces on the IQ80315 CRB can be tested and debugged using debug tools that plug into existing sockets. For example, a PCI bus analyzer, DDR logic analyzer card, Gigabit Ethernet tester, and USB tester can all be plugged into the respective sockets for interface debug. -
Page 39: Technical Reference
PCI request/grant signal mapping. • Table 18 describes the PCI IDSEL mapping. • Table 19 describes the interrupts. • Table 20 describes the GPIO assignments. • Table 21 describes the I C address map. ® Intel IQ80315 I/O Processor Evaluation Platform Board Manual... -
Page 40: Memory Map
448 KB 8-bit Reserved PCE3# 4E8D 0000–4E8D FFFF 64 KB 8-bit Rotary Switch PCE3# 4E8E 0000–4E8E FFFF 64 KB 8-bit Electronic Serial Number PCE3# 4E8F 0000–4E8F FFFF 64 KB 8-bit Battery Status ® Intel IQ80315 I/O Processor Evaluation Platform Board Manual... -
Page 41: Pci Request/Grant Mapping
AD18 31244 SATA Controller 0 AD19 31244 SATA Controller 1 PCI-X Bus 2 ® AD16 Intel 80314 I/O processor companion chip AD17 PCI Bus Connector 1 AD18 PCI Bus Connector 2 ® Intel IQ80315 I/O Processor Evaluation Platform Board Manual... -
Page 42: Interrupts
PCI bus 2 connector 1 INTB#, connector 2 INTC#, Debug header P2_INTC# PCI bus 2 connector 1 INTC#, connector 2 INTD#, Debug header P2_INTD# PCI bus 2 connector 1 INTD#, connector 2 INTA#, Debug header ® Intel IQ80315 I/O Processor Evaluation Platform Board Manual... -
Page 43: Gpio Assignments
DDR DIMM Serial Presence Detect EEPROM write protect 0x32 DDR DIMM Serial Presence Detect EEPROM write protect 0x50 DDR DIMM Serial Presence Detect EEPROM 0x51 DDR DIMM Serial Presence Detect EEPROM 0x52 DDR DIMM Serial Presence Detect EEPROM ® Intel IQ80315 I/O Processor Evaluation Platform Board Manual... -
Page 44: Software
4.2.1 Initialization Flow RedBoot* is in charge of booting the IQ80315 CRB to a known state where programs can be downloaded and debugged. The basic outline of how RedBoot boots the platform is described below. -
Page 45: Memory Map Setup By Redboot
Un-cached SDRAM Alias 0x80000000–0x9EFF0000 PCI1 MEM32 0x9EFF0000–0x9F000000 PCI1 I/O 0x9F000000–0xA0000000 PCI1 CFG 0xA0000000–0xB0000000 PCI1 PFM1 0xB0000000–0xC0000000 PCI1 PFM2 0xC0000000–0xDEFF0000 PCI2 MEM32 0xDEFF0000–0xDF000000 PCI2 I/O 0xDF000000–0xE0000000 PCI2 CFG 0xE0000000–0xF0000000 PCI2 PFM1 0xF0000000–0xFFFFFFFF PCI2 PFM2 ® Intel IQ80315 I/O Processor Evaluation Platform Board Manual... -
Page 46: Ethernet Communications
4.2.7 CompactFlash* The IQ80315 CRB has an 8-bit CompactFlash* (CF) interface that can be used to store data and executable images. The command cf info can be used to check the status of a CF card plugged into the socket. -
Page 47: General Peripherals
The product code register is a location inside the CPLD that holds the product identification for the IQ80315 CRB. The register read back 1 for a IQ80315 CRB. 4.2.9.3 Board Revision Register The board revision register is a location inside the CPLD that holds the stepping of the IQ80315 CRB. 4.2.9.4 CPLD Firmware Revision Register The CPLD F/W Revision Register is a location inside the CPLD that indicates the version of firmware that is currently programmed into the CPLD. -
Page 48: Diagnostics
Description: This test puts the 80200 processor into a tight cache loop with no hope of escape. • Read DDR0 and DDR1 Description: This test probes the SPD devices on Bank0 and Bank1 of the IQ80315 CRB and reports how memory is inserted into the banks. •... -
Page 49: Operating System Support
The RTC is not setup and calibrated by RedBoot, so calibration is left as an exercise for the user. • Fan Menu Description: This test permits the enabling and disabling of the fans on the IQ80315 CRB. There is no support for throttling the fans; they are either turned completely on or completely off. •... -
Page 50: Debug Software
Several software debug solutions are available for the IQ80315 CRB. Among them are: • code|lab* Debug software: Allows the downloading and debugging of applications through the JTAG interface. The FLASH memory of the IQ80315 CRB can also be programmed through code|lab. •... -
Page 51: Design Specifications
® Intel IQ80315 I/O Processor Evaluation Platform Appendix A Design Specifications Table 24 lists the specifications applicable to the IQ80315 CRB. Table 24. Design Specifications Reference Specification Version, Revision Date, The information is Name Title and Ownership available from… Version 2.03,... -
Page 52: Getting Started And Using The Debugger
Purpose ® The purpose of this appendix is to help the user to set up and become familiar with the Intel IQ80315 Customer Reference Board (IQ80315) and other related hardware and software. This appendix steps the user through an example program using: •... -
Page 53: Related Web Sites
® Intel IQ80315 I/O Processor Evaluation Platform B.1.4 Related Web Sites • Macraigor Systems*: http://www.ocdemon.net/ • Intel: — http://developer.intel.com/design/intelxscale/dev_tools/020523/index.htm — http://developer.intel.com/design/iio/iop315.htm — http://developer.intel.com/design/iio/docs/iop315.htm — http://developer.intel.com/design/iio/swsup/LED80315.htm ® Intel IQ80315 I/O Processor Evaluation Platform Board Manual... -
Page 54: Hardware And Software Setup
Section B.4.2, “Using Flash Programmer” on page • The IQ80315 is a standalone platform. Either place the board on an insulating mat, or mount it ® in a proper enclosure to prevent shorting out the board. Refer to Figure 2, “Intel... -
Page 55: Software Setup
To view the Code|Lab documentation, Adobe* Reader* is required. The latest version can be downloaded at http://www.adobe.com/products/acrobat/readstep2.html. Figure 16. Software Flow Diagram ATI* Code|Lab* Macraigor* DLL Debug Monitor Code Application Code Resides in the Flash Loads into Memory Flash Memory Evaluation Board ® Intel IQ80315 I/O Processor Evaluation Platform Board Manual... -
Page 56: New Project Setup
In the “Add Existing Item” window, use the drop-down menu under “Look In” to find the four files listed in step 7 on the hard drive. Select all four files and click “open”. The “Solution Explorer” window now shows these files under “Test80315”. ® Intel IQ80315 I/O Processor Evaluation Platform Board Manual... -
Page 57: Configuration
11. Click “Apply” and then click “OK”. 12. Under “Project Settings”, select Code|Lab Debugger ARM”. Set all four debug options to “false”. 13. In the “Solution Explorer” window, right click “Test80315” and select “Save Test80315”. ® Intel IQ80315 I/O Processor Evaluation Platform Board Manual... -
Page 58: Flashing With Jtag
• Standard elf (executable and linking format) ® RedBoot.s19 and RedBoot.srec are both srec files. Worcester.i32 is an ARM* BootMonitor* Intel Hex file. BootMonitor is an ARM version of a debug monitor, which is similar but not identical to RedBoot. -
Page 59: Using Flash Programmer
7. Select “Parallel Connection” and “LPT1”. 8. OCD Speeds must be “2” in both cases. Note: The IQ80315 works only with speeds 2 through 7. Speed 1 and speed 8 do not work. 9. Click “OK”. 10. Select “XScale 80200 (80315)”. -
Page 60: Debugging Out Of Flash
Rebuild cleans and builds. Clean deletes the old .o files in the project and build compiles, links, and produces the executable files. 3. When there are errors, carefully go back through Section B.3.2, “Configuration”. ® Intel IQ80315 I/O Processor Evaluation Platform Board Manual... -
Page 61: Running The Code|Lab* Debugger
3. Select menu File, Program Load Options, Load Executable and Symbols. a. Select “File, Open Program, Browse”. b. Browse to find c:\…\Test80315\O\Test80315.elf. 4. Click “Go” (80, 03, 31, and 15 cycle on the LEDs). 5. Cycle power on the board. ® Intel IQ80315 I/O Processor Evaluation Platform Board Manual... -
Page 62: Displaying Source Code
4. Click the “Remove all breakpoints” icon. 5. Press “Go” again, and notice that the program loop is infinite. 6. Press the “Halt” icon to stop execution. 7. Close the debugger, and cycle power to the board. ® Intel IQ80315 I/O Processor Evaluation Platform Board Manual... -
Page 63: Stepping Through The Code
Press window icons a second time to remove them from view. Again, there are many features of the debug environment not discussed here. Please see the Code|Lab manuals for a full description of debug features. ® Intel IQ80315 I/O Processor Evaluation Platform Board Manual... -
Page 64: Exploring The Code|Lab* Debug Windows
0x40000000, and click on the green arrow to the right (or press Enter). The vector table at the beginning of flash is displayed. Note: The tabs at the bottom allow you to select two memory regions to observe. ® Intel IQ80315 I/O Processor Evaluation Platform Board Manual... -
Page 65: Registers Window
B.8.8 Variables Window The “Variables” window behaves very similarly to the “Watch” window, except that it shows all active variables. Bring up the Variables window, click Animate, and watch the changes. ® Intel IQ80315 I/O Processor Evaluation Platform Board Manual... -
Page 66: Debugging Basics
(DBR0), one configurable data mask/address register (DBR1), and one data breakpoint control register (DBCON). The 80331 also supports a 256-entry trace buffer that records program execution information. The registers for controlling the trace buffer are located in CP14. ® Intel IQ80315 I/O Processor Evaluation Platform Board Manual... -
Page 67: Exception Trapping
Exception vector trap • Trace-buffer full break When a debug exception occurs, the processor actions depend on whether the debug unit is configured for Halt mode or Monitor mode. § § ® Intel IQ80315 I/O Processor Evaluation Platform Board Manual... - Page 68 ® Intel IQ80315 I/O Processor Evaluation Platform THIS PAGE INTENTIONALLY LEFT BLANK ® Intel IQ80315 I/O Processor Evaluation Platform Board Manual...
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