Intel iSBC 80 Hardware Reference Manual page 75

Principles of Operation
acting as a bus master or when not accessing its on-board
RAM, the iSBC 80/30 can act as a "slave" RAM device
in a multiple bus master system. When accessing its
on-board RAM, the on-board CPU has priority over any
attempt to access the on-board RAM via the Multibus. In
this situation, the bus access is held off until the CPU has
DUAL PORT CTL P·PERIODS PO
I
P1 P2
22.12 MHz
IL
P3
iSBC 80/30
completed its particular read or write operation. When a
bus access is in progress, the Dual Port Control Logic
enters the' 'slave" mode and any subsequent CPU request
will be held off until the slave mode is terminated. Figures
4 -9 and 4 -1 0 are timing diagrams for the Dual Port Con-
trollogic.
P4 P13
I
P14
I
P15
I
P16
I
P17
I
-
ON BD RAM RaT
0
I
I
, ( I
ADV MEM RDI OR WRTI
0
_ _ _ _
~--
_ _ - - - -_ _
~I~
_ _
-------------r
SLAVE RAM RaTI
0
SLAVE RAM RDI OR WRTI
0
FF A43·15 a
0
FF A55·9 a
0
FF A55·8
Q
0
FF A43·11
Q
0
FF A43·6
Q
0
OFF BD CSI
0
RAM RDI OR WRTI
0
RAM XACKI
0
RAM AACKI
0
Figure 4-9. Dual Port Control Bus Access Timing With CPU Lockout
611·9
4-10