Addressing; Initialization; Operation; Read Operation - Intel iSBC 80 Hardware Reference Manual

Intel isbc 80/30 single board computer hardware reference manual
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Programming Information
iSBC 80/30
Table 3-14. Typical PPI Initialization Subroutine
;INT PAR INITIALIZES PARALLEL PORTS.
;USES-NOTHING; DESTROYS-A.
INT PAR:
MVI
OUT
RET
END
3-29. ADDRESSING
A,92H
OEBH
The PPI uses four consecutive addresses (ES through EB)
for data transfer, obtaining the status of Port C (EA), and
for port control. (Refer to table 3-2.)
3-30. INITIALIZATION
To initialize the PPI, write a,control word to ES. -Refer to
figure 3-11 and table 3-14 and assume that the control
word is 92 (hexadecimal). This initializes the PLI as
follows:
a.
Mode Set Flag active
b.
Port A (ES) set to Mode 0 Input
c.
Port C (EA) upper set to Mode 0 Output
d.
Port B (E9) set to Mode 0 Input
e.
Port C (EA) lower set to Mode 0 Output
3-31. OPERATION
After the PPI has been initialized, the operation is simply
performing a read or a write to the appropriate port.
3-32. READ OPERATION.
A typical read subroutine
for Port A is given in table 3-15.
3-33. WRITE OPERATION.
A typical write sub-
routine for Port C is given in table 3-16. As shown in
figure 3-12, and of the Port C bits can be selectively set or
cleared by writing a control word to EB.
;MODE WORD TO PPI PORT A&B IN,C OUT
3-34. 8259A PIC PROGRAMMING
As described in paragraph 2-20, the PIC monitors the
interrupt requests from eight separate sources. When one
or more of the interrupt requests are active (true), the PIC
determines the following:
a.
Which input signal has the highest priority.
b.
Whether the input signal has a higher priority than
the interrupt presently being serviced by the main
processor. If so, the interrupt being serviced is in-
terrupted; if not, the input signal is held for later
output.
c.
Whether the interrupt input bit is masked.
Thus, the basic functions of the PIC are (1) resolve the
priority of interrupt requests and (2) issue a single inter-
rupt request to the SOS5A microprocessor (CPU) based on
that priority. The output of the PIC is applied directly to
the INTR input of the CPU. (Refer to paragraph 3-50.)
3-35. INTERRUPT PRIORITY MODES
The PIC' has two modes for resolving the priority of
interrupt inputs: (1) fully nested mode and (2) rotating
mode. The rotating mode has two variations: auto-rotating
and specific rotating.
3-36. FULLY NESTED MODE.
In this mode the PIC
input signals are assigned priority from 0 through 7. The
PIC operates in this mode unless specifically programmed
otherwise. Interrupt IRO has the highest priority and IR 7-
has the lowest priority. When an interrupt is acknow-
ledged, the highest priority request is available to the
CPU. Lower priority interrutps are inhibited; higher prior-
Table 3-15. Typical PPI Port Read Subroutine
3-14
;AREAD READS A BYTE FROM PORT A INTO REG A.
;USES-A; DESTROYS-A.
AREAD:
IN
RET
END
OE8H

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