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iSBC 80/30
Programming Information
PROGRAMMING FORMAT
ALTERNATE PROGRAMMING FORMAT
Step
Step
1
Mode Control Word
Counter n
1
Mode Control Word
Counter 0
2
LSB
Count Register Byte
Counter n
2
Mode Control Word
Counter 1
3
MSB
Count Register Byte
Counter n
3
Mode Control Word
Counter 2
4
LSB
Counter Register Byte
Counter 1
5
MSB
Count Register Byte
Counter 1
6
LSB
Count Register Byte
Counter 2
7
MSB
Count Register Byte
Counter 2
8
LSB
Count Register Byte
Counter 0
9
MSB
Count Register Byte
Counter 0
450-18
Figure 3-9.
PIT
Programming"Sequence Examples
a.
Mode 0: Interrupt on tenninal count. In this mode,
Counters 1 and 2 can be used for auxiliary functions
such as generating real-time interrupt intervals. After
the count value is loaded into the count register, the
counter output goes low and remains low until the
terminal count is reached. The output then goes high
until either the count register or the mode control
register is reloaded.
b.
Mode 1: Programmable one-shot. In this mode, the
output of Counter 1 and/or Counter 2 will go low on
the count following the rising edge of the GATE
input from Port EA. The output will go high on the
tenninal count. If a new count value is loaded while
the output is low, it will not affect the duration of
the one-shot pulse until the succeeding trigger. The
current count can be read at any time without af-
fecting the one-shot pulse. The one-shot is retrigger-
able, hence the output will remain low for the full
count after any rising edge of the gate input.
c.
Mode 2: Rate generator. In this mode, the output of
Counter 1 and/or Counter 2 will be low for one period
of the clock input. The period from one output pulse
to the next equals the number of input counts in the
• count register. If the count register is reloaded be-
tween output pulses, the present period will not be
affected but the subsequent period will reflect the
new value. The gate input, when low, will force the
output high. When the gate input goes high, the
counter will start from the initial count. Thus, the
gate input can be used to synchronize the counter.
When Mode 2 is set, the output will remain high
until after the count register is loaded; thus, the count
can be synchronized by software.
d.
Mode 3: Square wave generator. Mode 3, which is
the primary operating mode for Counter 2, is used for
generating Baud rate clock signals. In this mode, the
counter output remains high until one-half of the
count value in the count register has been decre-
mented (for even numbers). The output then goes
low for the other half of the count. If the value in the
count register is odd, the counter output is high for
(N
+
1)/2 counts, and low for (N -1)/2 counts.
e.
Mode 4. Software triggered strobe. After this mode is
set, the output will be high. When the count is
loaded, the counter begins counting. On tenninal
count, the output will go low for one input clock
period and then go high again. If the count register
is reloaded between output pulses, the present count
will not be affected, but the subsequent period will
reflect the new value. The count will be inhibited
~hile
the gate input is low. Reloading the count
register will restart the counting for the new value.
f.
Mode 5: Hardware triggered strobe. The counter
will start counting on the rising edge of the gate input
and the output will go low for one clock period when
3-9
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