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Principles of Operation
4-20. MEMORY READ TIMING.
Figure 4-6 shows
the timing of two successive memory read machine cy-
cles, the first without a Twait state and the second with
one Twait state. Disregarding the states of the SO and SI
lines, the timing during T
1
through T
3
is identical with the
opcode fetch machine cycle shown in figure 4-4. The
major difference between the opcode fetch and memory
read cycles is that an opcode fetch machine cycle requires
four or six T -states whereas the memory read machine
cycle requires only three T -states. One minor difference
between the two cycles is that the memory address used
for the opcode fetch cycle is always the contents of the
program counter (PC), which points to the current instruc-
tion; the address used for a memory read cycle can be one
of several origins. Also, the data read from memory is
placed into the appropriate register istead of the instruc-
tion register. Note that a T wait state is not imposed during
a read of on-board ROM/PROM.
4-21. I/O READ TIMING.
Figure 4-6 also illustrates
the timing of two successive I/O read machine cycles, the
first without a Twait state and the second with one Twait
state. With the exception of the IO/M status signal, the
timing of a memory read cycle and an I/O read
cycl~
is
identical. For an I/O read, IO/M is driven high to identify
that the current machine cycle is referencing an I/O port.
One other minor exception is that the address used for an
MR OR lOR
SIGNAL
T,
T2
T3
~
U- U-U-
elK
~
~
101M,
10/M·0 (MRI OR 1 (lORI.
s, •
1. SO· 0
SI.S0
I"-
~
~
A8"A'5
I"-
......
OUT
IN
~
Y.
~<
)-
AOo· A 07
AO-A7
°0·°7
l""'-
t
)
ALE
1 \
~
1.
iffi
r-
REAOY
'C
-~
iSBC
80/30
I/O read cycle is 'derived from the second byte of an IN
instruction; this address is dupilcated onto both the
A8-A15 and ADO-AD7lines. The data read from the I/O
port is always placed in the accumulator specified by the
IN instruction. Note that a T wait is not imposed during the
access of on-board I/O devices; T wait states are imposed
during the access of system I/O devices via the Multibus.
4-22. MEMORY WRITE TIMING.
Figure 4-7
shows the timing of two successive memory write
machine cycles, the first without a T wait, state. Again,
disregarding the states of the SO and SI lines" the timing
during T
1
is identical to the timing of an opcode fetch,
memory read, and I/O read cycles. The difference occurs,
however, at the end of T
1.
For instance, in a memory read
cycle the ADO-AD7 lines are disabled (high impedance)
at the beginning of T 2 in anticipation of the returned data.
In a memory write cycle, the ADO-AD7 lines are not
disabled and the data to be written into memory is placed
on these lines at the beginning ofT
2.
The Write
(WRI)
line
is driven low at this time to enable the addressed memory
device. During T2 the READY input is checked to deter-
mine if a Twait state is required. If the READY input is
low, Twait states are inserted until READY goes high.
During T
3 ,
the
WR!
line is driven high to disable the
addressed memory device and terminate the memory
write operation. Note that the contents on the address and
data lines do not change until the next T
1
state.
MR OR lOR
T,
T2
TWA IT
T3
U-
L I
u-
L I
~
10/M·0 (MRI OR 1 (lORI. SI • '. SO· 0
)
)
OUT
IN
~(-<
)
-<
Ao-A7
°0·°7
1 \
V-
~
f-
~
""
......
'L-- ~
,..,
"<----
~
Figure 4-6. Memory Read (or I/O Read) Machine Cycles
4-6
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