Priority Interrupts - Intel iSBC 80 Hardware Reference Manual

Preparation for Use
Table 2-7. 65K Page System Memory Selection
2-8
Low/(High)1
65K Address
System
Page No. Range 1
Memory
N/A 0
OOOO-FFFF
(Note 2) W5: *K-L
0-524K
0 OOOOO-OFFFF
(525-1048K) W5: K-A (80000-8FFFF)
1 10000-1 FFFF
W6: *B-C W5: K-B
(90000-9FFFF)
*D-E
2 20000-2FFFF
W5: K-C (AOOOO-AFFFF)
W6:
(B-E) 3 30000-3FFFF
(D-A) W5: K-D (BOOOO-BFFFF)
4 40000-4FFFF
W5:
K-E
(COOOO-CFFFF)
5 50000-5FFFF
W5: K-F (DOOOO-DFFFF)
6 60000-6FFFF
W5: K-G (EOOOO-EFFFF)
7 70000-7FFFF
W5: K-H (FOOOO-FFFFF)
NOTES:
1. Notation in parentheses applies to high (upper
524K) bytes of 20-bit system address space.
2. Systems without 20-bit address capability must
use jumper W5 in position *K-L.
* Default Jumper; disconnect if reconfiguration is
re~uired.
N/A
=
not applicable.
Table 2-8. 8K/16K Block Selection
Within 65K Page
Address Block Within 65K
8K or 16K Page (Refer to Table 2-7)
System Access
Jumper Block
8K
180-172 1st 8K
W4: *B-A
180-173 2nd 8K
180-174 3rd 8K
180-175 4th 8K
180-176 5th 8K
180-177 6th 8K
180-178 7th 8K
180-179 8th 8K
*180-171 No Access
16K 180-173 1st 16K
W4: B-C 180-175 2nd 16K
180-177 3rd 16K
180-179 4th 16K
*180-171 No Access
*Default jumper; disconnect if reconfiguration is desired.
iSBC 80/30
Finally, one jumper wire places the on-board RAM in the
desired 8K or 16K segment of the selected 65K page. To
access an 8K segment in Page 4 of the lower 524K, for
example, the 8K segment can be placed on any 8K
boundary 40000 (l st 8K), 42000 (2nd 8K), 44000
(3rd 8K), ... 4EOOO (8th 8K). To access a 16K segment
in Page 4 of the lower 524K, the 16K segment can be
placed on any 16K boundary 40000 Ost 16K), 44000
(2nd 16K), 48000 (3rd 16K), or4COOO (4th 16K). Figure
2-2 illustrates a step-by-step sequence for establishing
RAM addresses for a 20-bit address system.
2-20. PRIORITY INTERRUPTS
Table 2-9 lists the source (from) and destination (to) of the
interrupt matrix shown in figure 5 -2 sheet 7. For example,
note that the 8259A Programmable Interrupt Controller
(PIC) can handle eight positive-true interrupt requests
and, after resolving any priority contention, outputs an
interrupt request to the INTR input of the 8085A micro-
processor.
Study table 2-9 carefully while making reference to figure
5-2 sheet 7 before deciding on a definite priority config-
uration for the iSBC 80/30. There are two areas that
require some explanation: the 8085A TRAP and RST 7.5
interrupts.
Default jumper 137-145 grounds the TRAP interrupt
input to prevent the possibility of false interrupts being
generated by noise spikes. Since the TRAP interrupt is not
maskable, cannot be disabled by the program, and has the
highest priority, it should be used only to detect a cata-
strophic event such as a power failure or a bus failure.
The RST 7.5 interrupt input is edge-sensitive only and is
default jumpered to the COUNT OUT output of Counter
1. If it is desired to interrupt the 8085A if the Failsafe
Timer times out, remove jumper 123-138 (COUNT OUT)
and connect jumper 122-138 (BUS TIME OUT). (The
BUS TIME OUT signal is generated when the Failsafe
Timer is retriggered after timing out.)
NOTE
The 8259A PIC can be programmed to respond
to either edge-sensitive or level-sensitive inter-
rupt requests. If the PIC is programmed to re-
spond to edge-sensitive interrupt requests, the
PIC will respond only to a low-to-high transition
on anyone of the individual IR input lines.