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iSBC 80/30
SIGNAL
elK
101M,
SI,SO
ALE
Principles of Operation
Figure 4-4. Opcode Fetch Machine Cycle
Ml (OFI
SIGNAL
Tl
T2
TWAIT
T3
T4
T5
TS
to--
'-----J
\-.I \-.I \-.I
~
L-I
LJ
ClK
101M,
to--
)(
10/M
3
O,S1
3
1,SO-1
SI, SO
to--
I - -
)(
AS-A15
PCH
UNSPECIFIED
to--
I - -
OUT
IN
ADO-AD7
D<
PCl
~-(
0 0 -0 7 (DCXI
~
- - - - -
~----
10---
to--
!
)
ALE
r - \
to--
1
,'-'
R5
--'
~
READY
-c:::::=
~
~
'L-- N
Figure 4-5. Opcode Fetch Machine Cycle (With Wait)
READY input during T
2 •
If the READY input is high, the
CPU will proceed to T
3
as shown in figure 4-4. If the
READY input is low, however, the CPU will enter the
Twait state and stay there until READY goes high. When
READY goes high, the CPU will exit the Twait state and
enterT
3 .
The external effect of using the READY input is
to preserve the exact state of the CPU signals at the end of
T
3
for an integral number of clock periods before finishing
the machine cycle. This 'stretching' of the system timing,
in effect, increases the allowable access time for memory
or
VO
devices. By inserting Twait states, the CPU can
_ accommodate slower memory or slower
VO
devices. It
should be noted, however, that access to the on-board
ROM/PROM and
VO
ports does not impose a Twait state.
However, as mentioned previously, Twait states are im-
posed in certain instances when accessing on-board
RAM; Twait states are always imposed when accessing
system memory or
VO
devices via the Multibus.
4-5
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