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CHAPTER 3
PROGRAMMING INFORMATION
3-1. INTRODUCTION
This chapter lists the on-board memory and I/O address
assignments, describes the effects of a system initialize
command, and provides programming information for the
following programmable chips:
a.
Intel 8251A USART (Universal Synchronous/
Asynchronous Receiver/Transmitter) that controls
the serial I/O port.
b.
Intel 8253 PIT (Programmable Interval Timer) that
controls various frequency and timing functions.
c.
Intel 8255A PPI (Programmable Peripheral Inter-
face) that controls the three parallel I/O ports.
d.
Intel 8259A PIC (Programmable Interrupt Con-
troller) that can handle up to eight vectored pfi:ority
interrupts for the on-board 8085A microproces·sor
(CPU).
e.
Intel 8041/8741 UPI (Universal Peripheral Inter-
face).
This
chapt~r
also discusses the Intel 8085A Microproces-
sor interrupt capability. The instruction set for the 8085A
is included in Appendix A; a complete description of
programming with Intel's assembly language is given in
the 8080/8085' Assembly Language Programming Man-
ual, Order No. 9800310.
This chapter does not provide assembly language pro-
gramming information for the optional Intel 8041/8741
UPI (Universal Peripheral Interface). This information is
available in the UPI-41 User's Manual, Order No.
9800504A.
3-2. FAILSAFE TIMER
The 8085A microprocessor (CPU) expects an acknowl-
edge signal to be returned from the addressed I/O or
memory device in response to each Read or Write Com-
mand. The iSBC 80/30 includes a Failsafe Timer that is
triggered during T
1
of every machine cycle. If the Failsafe
Timer is enabled by hardwire jumper as described in table
2-4, and an acknowledge signal" is not received within
10 milliseconds, the Failsafe Timer will time out and
allow the CPU to exit the wait state. As described in
Chapter 2, provision is made so that the Failsafe Timer
output (BUS TIME OUT) can optionally be used to inter-
rupt the CPU and/or to drive a front panel indicator.
If the Failsafe Timer is not enabled, and an acknowledge
signal is not returned for any reason, the CPU will hang up
in a wait state. In this situation, the only way to free the
CPU is to initialize the system as described in paragraph
3-5.
3-3. MEMORY ADDRESSING
The iSBC 80/30 includes 16K of dynamic RAM and two
IC sockets to accommodate up to 8K of user-installed
ROM/PROM. The iSBC 80/30 features a two-port RAM
access arrangement in which the on-board RAM can be
accessed by the on-board 8085A microprocessor (CPU)
or by another bus master board via the Multibus. The
ROM/PROM can be accessed only by the CPU.
The on-board RAM can be accessed by another bus mas-
ter that currently has control of the Multibus. It should be
noted, however, that even though another bus master may
be continuously accessing the iSBC 80/30 on-board
RAM, this does not lock out the CPU from accessing the
on-board RAM. In this situation, Memory Commands
from the CPU and the controlling bus master are inter-
leaved. This, of course, will impose CPU wait states until
the current access by the controlling bus master is com-
pleted.
Addresses for CPU access of ROM/PROM and on-board
RAM are provided in table 3 -1. Note that the ROM!
PROM address space depends on the user's configura-
Table 3-1. On-Board Memory Addresses
(For CPU Access)
On-Board
Memory
Configuration
Legal Address
lllegal Address
ROM/PROM
One 1K x 8 chip
0OOO-03FF
0400-07FF
Two 1K x 8 chips
0OOO-07FF
-
ROM/PROM
One 2K x 8 chip
0OOO-07FF
0800-0FFF
Two 2K x 8 chips
OOOO-OFFF
-
ROM/PROM
One 4K x 8 chip
OOOO-OFFF
1000-1FFF
Two 4K x 8 chips
0OOO-1FFF
-
RAM
8K Access
2000-3FFF
None
*4000-5FFF
None
6000-7FFF
None
8000-9FFF
None
AOOO-BFFF
None
COOO-OFFF
None
EOOO-FFFF
None
RAM
*16K Access
*4000-7FFF
None
8000-BFFF
None
COOO-FFFF
None
*Oefault (factory connected) jumper; refer to paragraph 2-16. Address-
ing RAM outside the jumper-selected block results in an off-board
request via the Multibus.
3-1
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