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Interrupts
The table below recommends the logical interrupt mapping of interrupt
sources; it reflects a typical configuration, but these interrupts can be
changed by the user. Use the information to determine how to program
each interrupt. The actual interrupt map is defined using configuration
registers in the PIIX4 and the I/O controller. I/O Redirection Registers in
the I/O APIC are provided for each interrupt signal; the signals define
hardware interrupt signal characteristics for APIC messages sent to local
APIC(s).
To disable either IDE controller and reuse the interrupt
If you plan to disable either IDE controller to reuse the
interrupt for that controller, you must physically unplug the
IDE cable from the board connector (IDE0 or IDE1) if a
cable is present. Simply disabling the drive by configuring
the SCU option does not free up the interrupt.
Interrupt
INTR
NMI
IRQ1
Cascade
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ8_L
IRQ9
122
I/O APIC level
INT0
N/A
INT1
INT2
INT3
INT4
INT5
INT6
INT7
INT8
INT9
Description
Processor interrupt
NMI from DISMIC to processor
Keyboard interrupt
Interrupt signal from second 8259 in PIIX4
Serial port A or B interrupt from 87307VUL
device (user can configure)
Serial port A or B interrupt from 87307VUL
device (user can configure)
Parallel port
Diskette
Parallel port
RTC interrupt
Available (can be used by ISA bus)
Chapter 6 - Hardware Technical Reference
Continued
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