ICOP Technology ICOP-602X User Manual page 78

0F CMOS checksum calculation is done, DIAG byte written. CMOS init. To
begin (If " INIT CMOS IN EVERY BOOT IS SET").
10 CMOS initialization done (if any). CMOS status register about to init for
Date and Time.
11 CMOS Status register initialized. Going to disable DMA and Interrupt
controllers.
12 DMA controller #1,#2, interrupt controller #1,#2 disabled. About to
disable Video display and init port-B.
13 Video display is disabled and port-B is initialized. Chipset init/ auto
memory detection about to begin.
14 Chipset initialization/ auto memory detection over. 8254 timer test about
to start.
15 CH-2 timer test halfway. 8254 CH-2 timer test to be complete.
16 Ch-2 timer test over. 8254 CH-1 timer test to be complete.
17 CH-1 timer test over. 8254 CH-0 timer test to be complete.
18 CH-0 timer test over. About to start memory refresh.
19 Memory Refresh started. Memory Refresh test to be done next.
1A Memory Refresh line is toggling. Going to check 15 micro second ON/
OFF time.
1B Memory Refresh period 30 micro second test complete. Base 64K
memory test about to start.
20 Base 64k memory test started. Address line test to be done next.
21 Address line test passed. Going to do toggle parity.
22 Toggle parity over. Going for sequential data R/W test.
23 Base 64k sequential data R/W test passed. Any setup before Interrupt
vector init about to start.
24 Setup required before vector initialization complete. Interrupt vector
initialization about to begin.
25 Interrupt vector initialization done. Going to read I/O port of 8042 for
turbo switch (if any).
26 I/O port of 8042 is read. Going to initialize global data for turbo switch.
74 ICOP Embedded 386SX CPU ISA Half Size SBC User's Manual