Spi Control Registers; Table 12: Spi Interface Control Register - VersaLogic Viper Programmer's Reference Manual

FPGA Registers
SPI C
ONTROL
These are placed at the traditional offset 0x8 location. On-board SPI interface devices (DIOs,
ADC, and DAC for the EBX-38) and off-board SPX interface devices use this interface. The
EBX-38 is using the standard 2mm 2x7 pin header/14-pin SPX connector and can support up to
four devices and an interrupt input.
SPICONTROL

Table 12: SPI Interface Control Register

Bit Identifier
7 CPOL
6 CPHA
5-4 SPILEN(1:0)
3 MAN_SS
2-0 SS(2:0)
16
R
EGISTERS
Access Default
SPI clock polarity – Sets the SCLK idle state.
R/W 0 0 – SCLK idles low
1 – SCLK idles high
SPI clock phase – Sets the SCLK edge on which valid data will be read.
R/W 0
0 – Data is read on rising edge
1 – Data is read on falling edge
Determines the SPI frame length. This selection works in manual and
auto slave select modes.
00 – 8-bit
R/W 00
01 – 16-bit
10 – 24-bit
11 – 32-bit
Determines whether the slave select lines are asserted through the
user software or are automatically asserted by a write to SPIDATA3.
R/W 0
0 - The slave select operates automatically
1 - The slave select line is controlled manually through SPICONTROL
bits SS[2:0]
SPI Slave Device Selection:
000 – None
001 – SS0# (SPX slave device 0)
010 – SS1# (SPX slave device 1)
R/W 000
011 – SS2# (SPX slave device 2)
100 – SS3# (SPX slave device 3)
101 – ADC (analog input to digital conversion device)
110 – DIO (two digital I/O devices, differentiated by SPI addressing)
111 – DAC (digital to analog output conversion device)
Description
VL-EBX-38 Programmer's Reference Manual