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PCI Configuration and Device Map
Table 32.
PCI Map
Device
Hot Plug Controller
PCI Slot 1
PCI Slot 2
Embedded LVDS
Embedded VGA
PIIX4e
MAC
PB64
PB64
PB64
PB64
Hot Plug Controller
PCI Slot 3
PCI Slot 4
PCI Slot 5
PCI Slot 6
PID
Hot Plug Controller
PCI Slot 7
PCI Slot 8
Hot Plug Controller
PCI Slot 9
PCI Slot 10
Interrupts
The table below recommends the logical interrupt mapping of interrupt sources; it reflects a typical
configuration, but these interrupts can be changed by the user. Use the information to determine
how to program each interrupt. The actual interrupt map is defined using configuration registers in
the PIIX4E and the I/O controller. I/O Redirection Registers in the I/O APIC are provided for each
interrupt signal; the signals define hardware interrupt signal characteristics for APIC messages sent
to local APIC(s).
NOTE
To disable either IDE controller and reuse the interrupt: If you plan to
disable either IDE controller to reuse the interrupt for that controller, you
must physically unplug the IDE cable from the board connector (IDE0) if a
cable is present. Simply disabling the drive by configuring the SSU option
does not make the interrupt available.
SRPL8 Server System Product Guide
Segment
Device Number
A
00h
A
04h
A
05h
A
0Ah
A
0Ch
A
0Fh
A
14h
A
18h
A
19h
A
1Ah
A
1Bh
B
00h
B
04h
B
05h
B
06h
B
07h
B
09h
C
00h
C
04h
C
05h
D
00h
D
04h
D
05h
187
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