Figure 10. Frame Data Valid; Figure 11. Pixel Clock - Pulnix TM-7200 Operation Manual

OPERATION
FIGURE 10.
FIGURE 11.
TM-7200/TM-6200 High Resolution Digital CCD Camera
3.1.6 (c) Frame Data Valid and Odd/Even Field Valid
This is differential line-driven signal with EIA-422 format. It is active high during the transfer of each
frame data. During integration, both LDV (Line Data Valid) and FDV (Frame Data Valid) are kept low
and restart upon the completion of integration. When F1 is kept high, the camera outputs odd field data;
otherwise, even field data is output.
Frame Data Valid
VD
9H
NON-INTERLACE
FDV (DIGITAL)
FDV
FI
3.1.6 (d) Pixel Clock
Differential line-driven signal with EIA-422 format. The frequency is 40.068 MHz (standard).
Pixel Clock
DIGITAL DATA
N-5
PIXEL CLOCK
4nsec
69.9nsec.
VIDEO OUT.
16.4ms
1H
N-4
4H
1H
OB
N-3
N-2
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