Input Timing Diagram; Power On/Off Sequence - Advantech IDK-1110R-series User Manual

3.4.2

Input Timing Diagram

3.5

Power ON/OFF Sequence

VDD power and lamp on/off sequence is as follows. Interface signals are also shown
in the chart. Signals from any system shall be Hi-Z state or low level when VDD is off.
Power Sequence Timing(For IDK-1110R-40SVA1E)
Parameter
T1
T2
T3
Value
Min. Typ.
0.5 -
30 40
200 -
19
Unit
Max.
10 [ms]
50 [ms]
- [ms]
IDK-1110R User Manual