Processor Integrated I/O Module (Iio) - Intel S2600CO Family Technical Product Specification

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Functional Architecture Overview
What Mirroring primarily protects against is the possibility of an Uncorrectable ECC Error
occurring with critical data "in process". Without Mirroring, the system would be expected to
"Blue Screen" and halt, possibly with serious impact to operation. But with Mirroring Mode in
operation, an Uncorrectable ECC Error from one channel becomes a Mirroring Fail Over (MFO)
event instead, in which the IMC retrieves the correct data from the "mirror image" channel and
disables the failed channel. Since the ECC Error was corrected in the process of the MFO Event,
the ECC Error is demoted to a Correctable ECC Error. The channel pair becomes a single non-
redundant channel, but without impacting operations, and the Mirroring Fail Over Event is
logged to SEL to alert the user that there is memory hardware that has failed and needs to be
replaced.
3.2.3

Processor Integrated I/O Module (IIO)

The processor's integrated I/O module provides features traditionally supported through chipset
components. The integrated I/O module provides the following features:
PCI Express Interfaces: The integrated I/O module incorporates the PCI Express
interface and supports up to 40 lanes of PCI Express. Following are key attributes of the
PCI Express interface:
o Gen3 speeds up to 8 GT/s
o X16 interface bifurcated down to two x8 or four x4 (or combinations)
o X8 interface bifurcated down to two x4
DMI2 Interface to the PCH: The platform requires an interface to the legacy
Southbridge (PCH) which provides basic, legacy functions required for the server
platform and operating systems. Since only one PCH is required and allowed for the
system, any sockets which do not connect to PCH would use this port as a standard x4
PCI Express 2.0 interface.
Integrated IOAPIC: Provides support for PCI Express devices implementing legacy
interrupt messages without interrupt sharing
Non Transparent Bridge: PCI Express non-transparent bridge (NTB) acts as a gateway
that enables high performance, low overhead communication between two intelligent
subsystems; the local and the remote subsystems. The NTB allows a local processor to
independently configure and control the local subsystem, provides isolation of the local
host memory domain from the remote host memory domain while enabling status and
data exchange between the two domains.
QuickData Technology: Used for efficient, high bandwidth data movement
®
Intel
between two locations in memory or from memory to I/O.
30
Intel order number G42278-002
Intel® Server Board S2600CO Family TPS
Revision 1.0

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