Intel S2600CO Family Technical Product Specification page 141

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Appendix C: Integrated BMC Sensor Tables
Full Sensor Name
Sensor
(Sensor name in SDR)
Processor 1 Thermal Margin
74h
(P1 Therm Margin)
Processor 2 Thermal Margin
75h
(P2 Therm Margin)
Processor 1 Thermal
Control %
78h
(P1 Therm Ctrl %)
Processor 2 Thermal
Control %
79h
(P2 Therm Ctrl %)
Processor 1 ERR2 Timeout
7Ch
(P1 ERR2)
Processor 2 ERR2 Timeout
7Dh
(P2 ERR2)
Catastrophic Error
80h
(CATERR)
Processor0 MSID Mismatch
81h
(P0 MSID Mismatch)
Processor Population Fault
82h
(CPU Missing)
Processor1 MSID Mismatch
87h
(P1 MSID Mismatch)
Processor 1 VRD
Temperature
90h
(P1 VRD Hot)
130
Platform
Sensor Type
#
Applicability
Temperature
All
01h
Temperature
All
01h
Temperature
All
01h
Temperature
All
01h
Processor
All
07h
Processor
All
07h
Processor
All
07h
Processor
All
07h
Processor
All
07h
Processor
All
07h
Temperature
All
01h
Event /
Event Offset Triggers
Reading
Type
Threshold
-
01h
Threshold
-
01h
Threshold
[u] [c,nc]
01h
Threshold
[u] [c,nc]
01h
Digital
Discrete
01 – State Asserted
03h
Digital
Discrete
01 – State Asserted
03h
Digital
Discrete
01 – State Asserted
03h
Digital
Discrete
01 – State Asserted
03h
Digital
Discrete
01 – State Asserted
03h
Digital
Discrete
01 – State Asserted
03h
Digital
Discrete
01 - Limit exceeded
05h
Intel order number G42278-002
Intel® Server Board S2600CO Family TPS
Contrib. To
Assert
Readable
System Status
/ De-
Value /
assert
Offsets
-
-
Analog
-
-
Analog
nc =
As
Degraded
and
Analog
De
c = Non-fatal
nc =
As
Degraded
and
Analog
De
c = Non-fatal
As
fatal
and
De
As
fatal
and
De
As
fatal
and
De
As
fatal
and
De
As
Fatal
and
De
As
fatal
and
De
As
Non-fatal
and
De
Event
Rearm
Stand-
Data
by
R, T
A
R, T
A
Trig Offset
A
Trig Offset
A
Trig Offset
A
Trig Offset
A
Trig Offset
M
Trig Offset
M
Trig Offset
M
Trig Offset
M
Trig Offset
M
Revision 1.0

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