Table 6.
V
Static and Transient Tolerance for Processors with 4 MB L2 Cache
CC
I
(A)
CC
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
NOTES:
1. The loadline specification includes both static and transient limits except for overshoot allowed
as shown in
2. This table is intended to aid in reading discrete points on
3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE
lands. Voltage regulation feedback for voltage regulator circuits must be taken from processor
VCC and VSS lands. Refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery
Design Guidelines For Desktop LGA775 Socket for socket loadline guidelines and VR
implementation details.
4. Adherence to this loadline specification is required to ensure reliable processor operation.
22
Voltage Deviation from VID Setting (V)
Maximum Voltage
1.30 mΩ
0.000
-0.007
-0.013
-0.020
-0.026
-0.033
-0.039
-0.046
-0.052
-0.059
-0.065
-0.072
-0.078
-0.085
-0.091
-0.098
Section
2.6.3.
Typical Voltage
1.425 mΩ
-0.019
-0.026
-0.033
-0.040
-0.048
-0.055
-0.062
-0.069
-0.076
-0.083
-0.090
-0.097
-0.105
-0.112
-0.119
-0.126
Figure
1.
Electrical Specifications
1, 2, 3, 4
Minimum Voltage
1.55 mΩ
-0.038
-0.046
-0.054
-0.061
-0.069
-0.077
-0.085
-0.092
-0.100
-0.108
-0.116
-0.123
-0.131
-0.139
-0.147
-0.154
Datasheet
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