Intel E6420 - Core 2 Duo Dual-Core Processor Datasheet page 61

Land Listing and Signal Descriptions
Table 25.
Land
Land Name
#
C20
C21
C22
C23 VCCIOPLL
C24
C25
C26
C27
C28
C29
C30
D1 RESERVED
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14 RESERVED
D15
D16 RESERVED
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
Datasheet
Numerical Land
Assignment
Signal Buffer
Type
DBI3# Source Synch Input/Output
D58# Source Synch Input/Output
VSS Power/Other
Power/Other
VSS Power/Other
VTT Power/Other
VTT Power/Other
VTT Power/Other
VTT Power/Other
VTT Power/Other
VTT Power/Other
ADS# Common Clock Input/Output
VSS Power/Other
HIT# Common Clock Input/Output
VSS Power/Other
VSS Power/Other
D20# Source Synch Input/Output
D12# Source Synch Input/Output
VSS Power/Other
D22# Source Synch Input/Output
D15# Source Synch Input/Output
VSS Power/Other
D25# Source Synch Input/Output
VSS Power/Other
D49# Source Synch Input/Output
VSS Power/Other
DBI2# Source Synch Input/Output
D48# Source Synch Input/Output
VSS Power/Other
D46# Source Synch Input/Output
VCCPLL Power/Other
VSS Power/Other
VTT Power/Other
VTT Power/Other
VTT Power/Other
VTT Power/Other
Table 25.
Land
Direction Land Name
#
D29
D30
E2
E3 TRDY#
E4 HITM#
E5 FC20
E6 RESERVED
E7 RESERVED
E8
E9 D19#
E10 D21#
E11
E12 DSTBP1#
E13 D26#
E14
E15 D33#
E16 D34#
E17
E18 D39#
E19 D40#
E20
E21 D42#
E22 D45#
E23 RESERVED
E24 FC10
E25
E26
E27
E28
E29 FC26
F2
F3 BR0#
F4
F5 RS1#
F6 FC21
F7
F8 D17#
F9 D18#
F10
Numerical Land
Assignment
Signal Buffer
Direction
Type
VTT Power/Other
VTT Power/Other
VSS Power/Other
Common Clock
Common Clock Input/Output
Power/Other
VSS Power/Other
Source Synch Input/Output
Source Synch Input/Output
VSS Power/Other
Source Synch Input/Output
Source Synch Input/Output
VSS Power/Other
Source Synch Input/Output
Source Synch Input/Output
VSS Power/Other
Source Synch Input/Output
Source Synch Input/Output
VSS Power/Other
Source Synch Input/Output
Source Synch Input/Output
Power/Other
VSS Power/Other
VSS Power/Other
VSS Power/Other
VSS Power/Other
Power/Other
FC5 Power/Other
Common Clock Input/Output
VSS Power/Other
Common Clock
Power/Other
VSS Power/Other
Source Synch Input/Output
Source Synch Input/Output
VSS Power/Other
Input
Input
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