Intel E6420 - Core 2 Duo Dual-Core Processor Datasheet page 76

Table 26. Signal Description (Sheet 1 of 9)
Name
RESERVED
RS[2:0]#
SKTOCC#
SMI#
STPCLK#
TCK
TDI
TDO
TESTHI[13:0]
THERMDA
THERMDC
76
Type
All RESERVED lands must remain unconnected. Connection of these
lands to V , V
CC SS
can result in component malfunction or incompatibility with future
processors.
RS[2:0]# (Response Status) are driven by the response agent (the
agent responsible for completion of the current transaction), and
Input
must connect the appropriate pins/lands of all processor FSB
agents.
SKTOCC# (Socket Occupied) will be pulled to ground by the
Output processor. System board designers may use this signal to determine
if the processor is present.
SMI# (System Management Interrupt) is asserted asynchronously
by system logic. On accepting a System Management Interrupt, the
processor saves the current state and enter System Management
Mode (SMM). An SMI Acknowledge transaction is issued, and the
Input
processor begins program execution from the SMM handler.
If SMI# is asserted during the de-assertion of RESET#, the
processor will tri-state its outputs.
STPCLK# (Stop Clock), when asserted, causes the processor to
enter a low power Stop-Grant state. The processor issues a Stop-
Grant Acknowledge transaction, and stops providing internal clock
signals to all processor core units except the FSB and APIC units.
Input The processor continues to snoop bus transactions and service
interrupts while in Stop-Grant state. When STPCLK# is de-asserted,
the processor restarts its internal clock to all units and resumes
execution. The assertion of STPCLK# has no effect on the bus clock;
STPCLK# is an asynchronous input.
TCK (Test Clock) provides the clock input for the processor Test Bus
Input
(also known as the Test Access Port).
TDI (Test Data In) transfers serial test data into the processor. TDI
Input
provides the serial input needed for JTAG specification support.
TDO (Test Data Out) transfers serial test data out of the processor.
Output TDO provides the serial output needed for JTAG specification
support.
TESTHI[13:0] must be connected to the processor's appropriate
power source (refer to VTT_OUT_LEFT and VTT_OUT_RIGHT signal
Input
description) through a resistor for proper processor operation. See
Section 2.5 for more details.
Other Thermal Diode Anode. See
Other Thermal Diode Cathode. See
Land Listing and Signal Descriptions
Description
, V , or to any other signal (including each other)
TT
Section 5.3.
Section 5.3.
Datasheet