Intel SL8J6 - Pentium 4 Processor Datasheet page 25

Table 11. V Static and Transient Tolerance for Loadline B
CC
Icc (A)
0
5
10
15
20
25
30
35
40
45
50
55
60
65
70
75
78
NOTES:
1. The loadline specification includes both static and transient limits except for overshoot allowed
as shown in
2. This table is intended to aid in reading discrete points on
3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE
pins. Voltage regulation feedback for voltage regulator circuits must be taken from processor
VCC and VSS pins. Refer to the Voltage Regulator-Down (VRD) 10.0 Design Guide for socket
loadline guidelines and VR implementation details for 478_VR_CONFIG_B.
Datasheet
Voltage Deviation from VID Setting (V)
Maximum Voltage
0.000
-0.007
-0.015
-0.022
-0.029
-0.036
-0.044
-0.051
-0.058
-0.065
-0.073
-0.080
-0.087
-0.094
-0.102
-0.109
-0.113
Section 2.11.
1,2,3
Typical Voltage Minimum Voltage
-0.025
-0.033
-0.041
-0.049
-0.058
-0.066
-0.074
-0.082
-0.090
-0.098
-0.106
-0.114
-0.123
-0.131
-0.139
-0.147
-0.152
Figure 3.
Electrical Specifications
-0.050
-0.059
-0.068
-0.077
-0.086
-0.095
-0.104
-0.113
-0.122
-0.131
-0.140
-0.149
-0.158
-0.167
-0.176
-0.185
-0.190
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