Intel SL8J6 - Pentium 4 Processor Datasheet page 59

Table 25. Signal Description (Page 6 of 8)
Name
PROCHOT#
PWRGOOD
REQ[4:0]#
RESET#
RS[2:0]#
RSP#
SKTOCC#
SLP#
Datasheet
Type
As an output, PROCHOT# (Processor Hot) will go active when the processor
temperature monitoring sensor detects that the processor has reached its
Input/ maximum safe operating temperature. This indicates that the processor Thermal
Output Control Circuit (TCC) has been activated, if enabled. As an input, assertion of
PROCHOT# by the system activates the TCC, if enabled. The TCC remains
active until the system de-asserts PROCHOT#.
PWRGOOD (Power Good) is a processor input. The processor requires this
signal to be a clean indication that the clocks and power supplies are stable and
within their specifications. The term 'Clean' implies that the signal will remain low
(capable of sinking leakage current), without glitches, from the time that the
power supplies are turned on until they come within specification. The signal
must then transition monotonically to a high state. PWRGOOD can be driven
Input
inactive at any time, but clocks and power must again be stable before a
subsequent rising edge of PWRGOOD.
The PWRGOOD signal must be supplied to the processor; it is used to protect
internal circuits against voltage sequencing issues. It should be driven high
throughout boundary scan operation.
REQ[4:0]# (Request Command) must connect the appropriate pins of all
processor FSB agents. They are asserted by the current bus owner to define the
Input/
currently active transaction type. These signals are source synchronous to
Output
ADSTB0#. Refer to the AP[1:0]# signal description for a details on parity
checking of these signals.
Asserting the RESET# signal resets the processor to a known state and
invalidates its internal caches without writing back any of their contents. For a
power-on Reset, RESET# must stay active for at least 1 ms after V
have reached their proper specifications. On observing active RESET#, all FSB
agents will de-assert their outputs within two clocks. RESET# must not be kept
asserted for more than 10 ms while PWRGOOD is asserted.
Input
A number of bus signals are sampled at the active-to-inactive transition of
RESET# for power-on configuration. These configuration options are described
in the Section 6.1.
This signal does not have on-die termination and must be terminated on
the system board.
RS[2:0]# (Response Status) are driven by the response agent (the agent
Input responsible for completion of the current transaction), and must connect the
appropriate pins of all processor FSB agents.
RSP# (Response Parity) is driven by the response agent (the agent responsible
for completion of the current transaction) during assertion of RS[2:0]#, the
signals for which RSP# provides parity protection. It must connect to the
appropriate pins of all processor FSB agents.
Input
A correct parity signal is high if an even number of covered signals are low and
low if an odd number of covered signals are low. While RS[2:0]# = 000, RSP# is
also high, since this indicates it is not being driven by any agent guaranteeing
correct parity.
SKTOCC# (Socket Occupied) will be pulled to ground by the processor. System
Output
board designers may use this pin to determine if the processor is present.
SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to enter
the Sleep state. During Sleep state, the processor stops providing internal clock
signals to all units, leaving only the Phase-Locked Loop (PLL) still operating.
Processors in this state will not recognize snoops or interrupts. The processor
Input
will recognize only assertion of the RESET# signal, and de-assertion of SLP#. If
SLP# is de-asserted, the processor exits the Sleep state and returns to Stop-
Grant state, restarting its internal clock signals to the bus and processor core
units.
Pin List and Signal Description
Description
and BCLK
CC
59