Table of Contents
Advertisement
User Manual
Table 15-6: CPUID Standard Feature implementation
A.4.2 CPUID AMD Feature Support (Extended Function
Table 15-7 shows the extended feature bits returned by the AweSim CPU processor
model and which features are fully ( ) or only partially ( ) implemented and
supported. A
indicates that the returned feature bit is zero and this feature is not
implemented and not supported.
Feature
Floating-Point Unit
Virtual Mode Extensions
1
Debugging Extensions
Page-Size Extension
Time Stamp Counter
AMD Model-Specific Registers
Page Address Extensions
Machine Check Exception
CMPXCHG8B Instruction
APIC
SYSCALL and SYSRET
Memory Type Range Registers
Page Global Extension
Machine Check Architecture
Conditional Move Instruction
Page Attribute Table
Page Size Extensions (PSE-36)
No-execute page protection
2
SEM
AMD extensions to MMX™
MMX™
FXSAVE/FXRSTOR
Fast FXSAVE/FXRSTOR
1 GB Paging feature
RDTSCP
2
Long Mode
AMD Extensions to 3DNow!™
3DNow! Instructions
Virtualization Technology
Table 15-7: CPUID Extended Feature implementation
1
Only read and write to debug registers is supported, side effects are not implemented.
2
Controlled by FUSE state.
Appendix A
AMD Confidential
0x80000001)
th
7
Generation
Generation
September 12
th
th
8
8
Generation
(Base)
Pre.-Rev. F
th
, 2008
th
8
Generation
Rev. F
187
Advertisement
Table of Contents
