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<Event Device="CPU0" Type="MEMW" ICount="3133971259"
Address="00000000000A88B2" Size="1">
<Data Length="1" Value="01" />
</Event>
Defines a Memory Read or Memory Write event. MEMR and MEMW are recorded for
MMIO ranges.
7.22.2.2 XTR Binary File Contents
XTR Binary file contains the memory image of the system just before the XTR Record
started. The binary file contains multiple records where each record contains has the
following structure:
Physical Address Of the Page: 8 bytes
Count of Bytes in this Page: 4 Bytes
Data Of the Page: Count of Bytes earlier
Currently XTR only supports page size of 4096 bytes. Both the DIMM and MMIO may
be present in the XTR Binary file. The last record in the binary file must have a count of
zero to indicate end of memory image.
7.22.3 ModeFlags
ModeFlags defines some of the states of the CPU that are important for execution. The
upper 32 bits store the Execution Control flags e.g. HLT and <ignore interrupts for 1
instruction when we change stack segment>. The lower 32 bits is redundant from other
initialization values in the XTR initialization but is there to maintain code consistency.
Table 7-7 shows the Execution Control Flags (upper 32 bit):
Execution Control Flag
BIUI_LOCK
BIUI_RESET
BIUI_INIT
BIUI_INTR
BIUI_NMI
BIUI_SMI
BIUI_IGNNE
BIUI_A20M
BIUI_PAUSE
BIUI_HOLD
BIUI_UNUSED
BIUI_STOP
Table 7-8 shows other internal execution control flags. Some flags may be AweSim
specific.
Execution Control Flag
ECF_SMCRESTART
ECF_GENEXCEPTION
ECF_VINTR
112
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Value
0x00000001
0x00000002
0x00000004
0x00000008
0x00000010
0x00000020
0x00000040
0x00000080
0x00000100
0x00000200
0x00000400
0x00000800
Table 7-7: Execution Control Flags
Value
0x00001000
SMC detected in current translation (restart required).
0x00002000
SVM virtual interrupt pending
0x00004000
INIT pin
September 12
Description
Bus is locked
Processor RESET pin.
INIT pin
Interrupt
NMI
SMI
Floating point IGNNE
A20Mask
PAUSE
HOLD
Unused
Pseudo pin that stops simulation
Description
Chapter 7: Device Configuration
h
, 2008
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