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User Manual
Mnemonic
XOR reg16,reg/mem16
XOR reg32,reg/mem32
XOR reg64,reg/mem64
A.6.3 System Instructions
This chapter describes the function, mnemonic syntax and opcodes that the simulator
simulates. The system instructions are used to establish the operating mode, access
processor resources, handle program and system errors, and manage memory. Many of
these instructions can only be executed by privileged software, such as the operating
system kernel and interrupt handlers, that run at the highest privilege level. Only system
instructions can access certain processor resources, such as the control registers, model-
specific register, and debug registers.
Mnemonic
ARPL reg/mem16,reg16
CLI
CLTS
HLT
INT 3
INVD
INVLPG mem8
IRET
IRETD
IRETQ
LAR reg16,reg/mem16
LAR reg32,reg/mem16
1
In 64-bit mode, this opcode (0x63) is used for the MOVSXD instruction.
2
See Section A.6.3.1, "INT – Interrupt to Vector", on page 203.
3
See Section A.6.3.2, "IRET – Return from Interrupt", on page 203.
Appendix A
AMD Confidential
Instruction
Opcode
33 /r
33 /r
33 /r
Table 15-8: General-Purpose Instruction Reference
Instruction
Opcode
Adjust
the
selector to a level not less than the RPL of
63 /r
the segment selector specifies in the 16-bit
source register.
FA
Clear the interrupt flag (IF) to zero.
Clear the task-switched (TS) flag in CR0 to
0F 06
0.
F4
Halt instruction execution.
CC
Trap to debugger at interrupt 3.
Flush internal caches and trigger external
0F 08
cache flushes.
Invalidate
0F 01 /7
containing a specified memory location.
CF
Return from interrupt (16-bit operand size).
CF
Return from interrupt (32-bit operand size).
CF
Return from interrupt (64-bit operand size).
Reads the GDT/LDT descriptor referenced by
the
16-bit
0F 02 /r
attributes with FF00h and saves the result
in the 16-bit destination register.
Reads the GDT/LDT descriptor referenced by
the
16-bit
0F 02 /r
attributes
result in the 32-bit destination register.
Description
XOR
the
contents
destination
register
contents
of
a
16-bit
memory operand and store the result
in the destination.
XOR
the
contents
destination
register
contents
of
a
32-bit
memory operand and store the result
in the destination.
XOR
the
contents
destination
register
contents
of
a
64-bit
memory operand and store the result
in the destination.
Description
RPL
of
a
destination
the
TLB
entry
for
source
operand
source
operand
with
00FFFF00h
and
th
September 12
, 2008
Supported
of
a
16-bit
with
the
register
or
of
a
32-bit
with
the
register
or
of
a
64-bit
with
the
register
or
Supported
segment
1
2
the
page
3
3
3
masks
the
masks
the
saves
the
221
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