National Semiconductor CP3BT26 User Manual page 94

Table 40 USB Controller Registers
Name Address
EPC0 FF FDC0h
EPC1 FF FDD0h
EPC2 FF FDD8h
EPC3 FF FDE0h
EPC4 FF FDDE8h
EPC5 FF FDF0h
EPC6 FF FDF8h
TXS0 FF FDC4h
TXS1 FF FDD4h
TXS2 FF FDE4h
TXS3 FF FDF4h
TXC0 FF FDC6h
TXC1 FF FDD6
TXC2 FF FDE6h
TXC3 FF FDF6h
TXD0 FF FDC2h
TXD1 FF FDD2h
TXD2 FF FDE2h
TXD3 FF FDF2h
RXS0 FF FDCCh
RXS1 FF FDDCh
RXS2 FF FDECh
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Description
Endpoint Control 0
Register
Endpoint Control 1
Register
Endpoint Control 2
Register
Endpoint Control 3
Register
Endpoint Control 4
Register
Endpoint Control 5
Register
Endpoint Control 6
Register
Transmit Status 0
Register
Transmit Status 1
Register
Transmit Status 2
18.3.1
Register
The MCNTRL register controls the main functions of the
Transmit Status 3
CR16 USB node. The MCNTRL register provides read/write
Register
access from the CPU bus. Reserved bits must be written
with 0, and they return 0 when read. It is clear after reset.
Transmit Command 0
Register
Transmit Command 1
Register
Transmit Command 2
Register
USBEN
Transmit Command 3
Register
Transmit Data 0
Register
Transmit Data 1
Register
Transmit Data 2
Register
Transmit Data 3
Register
Receive Status 0
Register
Receive Status 1
Register
Receive Status 2
Register
94
Table 40 USB Controller Registers
Name Address
RXS3 FF FDFCh
RXC0 FF FDCEh
RXC1 FF FDDEh
RXC2 FF FDEEh
RXC3 FF FDFEh
RXD0 FF FDCAh
RXD1 FF FDDAh
RXD2 FF FDEAh
RXD3 FF FDFAh
Main Control Register (MCNTRL)
7 4
Reserved
The USB Enable controls whether the USB
module is enabled. If the USB module is dis-
abled, the 48 MHz clock within the USB node
is stopped, all USB registers are initialized to
their reset state, and the USB transceiver forc-
es SE0 on the bus to prevent the hub from de-
tected the USB node. The USBEN bit is clear
after reset.
0 – The USB module is disabled.
1 – The USB module is enabled.
Description
Receive Status 3
Register
Receive Command 0
Register
Receive Command 1
Register
Receive Command 2
Register
Receive Command 3
Register
Receive Data 0
Register
Receive Data 2
Register
Receive Data 2
Register
Receive Data 3
Register
3 2 1 0
NAT Reserved USBEN