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Data bits are sensed by taking a majority vote of three sam-
ples latched near the midpoint of each baud (bit time). Nor-
mally, the position of the samples within the baud is
determined automatically, but software can override the au-
tomatic selection by setting the USMD bit in the UnMDSL2
register and programming the UnSPOS register.
Serial data input on the RXD pin is shifted into the RSFT
register. On receiving the complete character, the contents
16
16
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Control and
Error Detection
Parity
Generator/Checker
Figure 76. UART Block Diagram
1
2
3
4
5
6
Sample
STARTBIT
1
2
3
4
5
6
DATABIT
Figure 77. UART Asynchronous Communication
of the RSFT register are copied into the UnRBUF register
and the Receive Buffer Full bit (URBF) is set. The URBF bit
is automatically cleared when software reads the character
from the URBUF register. The RSFT register is not software
accessible.
Transmitter
Baud Clock
Flow Control
System Clock
Baud Rate
Generator
Baud Clock
Receiver
7
8
9
10
11
12
Sample
7
8
9
10
11
12
Sample
164
TXD
RTS
Logic
CTS
CKX
RXD
DS060
13
14
15
16
1
DATA (LSB)
13
14
15
16
1
DS061
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