National Semiconductor CP3BT26 User Manual page 21

Mnemonic
ASHUD Rsrc/imm, RPdest
LSHi Rsrc/imm, Rdest
LSHD Rsrc/imm, RPdest
SBITi Iposition, disp(Rbase)
Iposition, disp(RPbase)
Iposition, (Rindex)disp(RPbasex)
Iposition, abs
Iposition, (Rindex)abs
CBITi Iposition, disp(Rbase)
Iposition, disp(RPbase)
Iposition, (Rindex)disp(RPbasex)
Iposition, abs
Iposition, (Rindex)abs
TBIT Rposition/imm, Rsrc
TBITi
Iposition, disp(Rbase)
Iposition, disp(RPbase)
Iposition, (Rindex)disp(RPbasex)
Iposition, abs
Iposition, (Rindex)abs
LPR Rsrc, Rproc
LPRD RPsrc, Rprocd
SPR Rproc, Rdest
SPRD Rprocd, RPdest
Bcond disp9
disp17
disp24
BAL RPlink, disp24
BR disp9
disp17
disp24
EXCP vector
Jcond RPtarget
JAL RA, RPtarget,
RPlink, RPtarget
JUMP RPtarget
JUSR RPtarget
Table 5 Instruction Set Summary
Operands
Arithmetic left/right shift
Logical left/right shift
Logical left/right shift
Set a bit in memory
(Because this instruction treats the destination as a read-
modify-write operand, it not be used to set bits in write-
only registers.)
Clear a bit in memory
Test a bit in a register
Test a bit in memory
Load processor register
Load double processor register
Store processor register
Store 32-bit processor register
Conditional branch
Branch and link
Branch
Trap (vector)
Conditional Jump to a large address
Jump and link to a large address
Jump
Jump and set PSR.U
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Description
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