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Bus State
T1
CLK
A[21:0]
A22 ('13 only)
SELx
SELy
(y ≠ x)
D[15:0]
RD
WR[1:0]
Figure 131. Early Write Between Normal Read Cycles (No Wait States)
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Normal Read
T2
T1
t
t
, t
4
4
12
t
, t
t
, t
5
12
5
12
t
3
In
t
, t
5
12
t
, t
5
12
t
9
t
, t
6
13
Early Write
T2
T3
t
, t
8
12
Out
t
, t
6
13
264
Normal Read
T1
T2
t
, t
t
, t
5
12
5
t
2
t
1
In
12
DS124
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