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parity bit is generated and transmitted following the eight
data bits.
Start
2
Bit
Start
2a
Bit
Start
2b
Bit
Start
2c
Bit
Figure 80. 8-Bit Data Frame Options
The format shown in Figure 81 consists of one start bit, nine
data bits, and one or two stop bits. This format also supports
the UART attention feature. When operating in this format,
all eight bits of UnTBUF and UnRBUF are used for data.
The ninth data bit is transmitted and received using two bits
in the control registers, called UXB9 and URB9. Parity is not
generated or verified in this mode.
Start
3
Bit
Start
3a
Bit
Figure 81. 9-bit Data Frame Options
22.2.6
Baud Rate Generator
The Baud Rate Generator creates the basic baud clock from
the System Clock. The System Clock is passed through a
two-stage divider chain consisting of a 5-bit baud rate pres-
caler (UnPSC) and an 11-bit baud rate divisor (UnDIV).
The relationship between the 5-bit prescaler select (UnP-
SC) setting and the prescaler factors is shown in Table 69.
Table 69 Prescaler Factors
Prescaler Select
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
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8-Bit Data
1S
8-Bit Data
2S
8-Bit Data
PA
1S
8-Bit Data
PA
2S
DS064
9-Bit Data
1S
9-Bit Data
2S
DS065
Prescaler Factor
No clock
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
Table 69 Prescaler Factors (Continued)
Prescaler Select
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
A prescaler factor of zero corresponds to "no clock." The "no
clock" condition is the UART power down mode, in which the
UART clock is turned off to reduce power consumption.
Software must select the "no clock" condition before enter-
ing a new baud rate. Otherwise, it could cause incorrect
data to be received or transmitted. The UnPSR register
must contain a value other than zero when an external clock
is used at CKX.
22.2.7
Interrupts
The UART is capable of generating interrupts on:
Receive Buffer Full
Receive Error
Transmit Buffer Empty
166
Prescaler Factor
6
6.5
7
7.5
8
8.5
9
9.5
10
10.5
11
11.5
12
12.5
13
13.5
14
14.5
15
15.5
16
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