National Semiconductor CP3BT26 User Manual page 259

0.7VCC
SDA
0.3VCC
0.7VCC
SCL
0.3VCC
Note: In the timing tables the parameter name is added with an "o" for output signal timing and "i" for input signal timing.
Figure 125. ACB Signals (SDA and SCL) Timing
SDA
t
DLCs
SCL
t
CSTOs
Note: In the timing tables the parameter name is added with an "o" for output signal timing and "i" for input signal timing.
Figure 126. ACB Start and Stop Condition Timing
SDA
SCL
Note: In the timing tables the parameter name is added with an "o" for output signal timing
and "i" for input signal timing.
Figure 127. ACB Start Condition Timing
t
SDAr
t
SCLr
Stop Condition
t
BUF
Start Condition
t t
CSTRs
t
DHCs
259
0.7VCC
0.3VCC
t
SDAf
0.7VCC
0.3VCC
t
SCLf
Start Condition
t
CSTRh
CSTRh
DS108
DS106
DS107
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