Table of Contents
Advertisement
22.4.2
Synchronous Mode
Synchronous mode is only available for the UART0 module.
When synchronous mode is selected and the UCKS bit is
set, the UART operates from a clock received on the CKX
pin. When the UCKS bit is clear, the UART uses the clock
from the internal baud rate generator which is also driven on
the CKX pin. When the internal baud rate generator is used,
the equation for calculating the baud rate is:
BR
=
SYS_CLK = 48 MHz
Baud
Rate
O
N
300
16
2000
600
16
2000
1200
16
1250
1800
7
401
2000
16
1500
2400
16
1250
3600
8
1111
4800
16
625
7200
12
101
9600
16
125
14400
11
202
19200
10
250
38400
10
125
56000
7
49
115200
7
17
128000
15
25
230400
13
16
345600
9
1
460800
13
8
576000
8
7
691200
10
7
806400
7
1
921600
13
4
1105920
11
4
1382400
10
1
1536000
9
1
SYS_CLK
---------------------------- -
(
×
×
)
2
N P
Table 71 Baud Rate Programming
SYS_CLK = 24 MHz
P
%err
O
N
5.0
0.00
16
2000
2.5
0.00
16
1250
2.0
0.00
16
1250
9.5
0.00
8
1111
1.0
0.00
16
750
1.0
0.00
16
625
1.5
0.01
12
101
1.0
0.00
16
125
5.5
0.01
11
303
2.5
0.00
10
250
1.5
0.01
11
101
1.0
0.00
10
125
1.0
0.00
10
25
2.5
0.04
13
33
3.5
0.04
13
16
1.0
0.00
15
5
1.0
0.16
13
8
15.5 0.44
10
7
1.0
0.16
13
4
1.5
0.79
12
1
1.0
0.79
10
1
8.5
0.04
15
2
1.0
0.16
13
2
1.0
1.36
11
2
3.5
0.79
7
1
3.5
0.79
8
2
where BR is the baud rate, SYS_CLK is the System Clock,
N is the value of the baud rate divisor + 1, and P is the pres-
caler divide factor selected by the value in the UnPSR reg-
ister. Oversampling is not used in synchronous mode.
Use the same procedure to determine the values of N and
P as in the asynchronous mode. In this case, however, only
integer prescaler values are allowed.
SYS_CLK = 12 MHz
P
%err
O
N
2.5
0.00
16
1250
2.0
0.00
16
1250
1.0
0.00
16
625
1.5
0.01
12
101
1.0
0.00
16
250
1.0
0.00
16
125
5.5
0.01
11
202
2.5
0.00
10
250
1.0
0.01
11
101
1.0
0.00
10
125
1.5
0.01
14
17
1.0
0.00
10
25
2.5
0.00
16
13
1.0
0.10
13
11
1.0
0.16
13
8
2.5
0.00
11
1
1.0
0.16
13
4
1.0
0.79
10
1
1.0
0.16
13
2
3.5
0.79
14
1
3.5
0.79
7
1
1.0
0.79
10
1
1.0
0.16
13
1
1.0
1.36
2.5
0.79
1.0
2.34
173
SYS_CLK = 10 MHz
P
%err
O
N
2.0
0.00
13
1282
1.0
0.00
13
1282
1.0
0.00
13
641
5.5
0.01
12
463
1.5
0.00
16
125
2.5
0.00
9
463
1.5
0.01
11
101
1.0
0.00
7
119
1.5
0.01
10
139
1.0
0.00
7
149
3.5
0.04
14
33
2.5
0.00
16
13
1.5
0.16
8
13
1.5
0.10
7
17
1.0
0.16
7
5
8.5
0.27
12
1
1.0
0.16
11
4
3.5
0.79
1.0
0.16
11
2
1.5
0.79
7
1
2.5
0.79
1.5
0.79
1.0
0.16
9
1
www.national.com
P
%err
2.0
0.00
1.0
0.00
1.0
0.00
1.0
0.01
2.5
0.00
1.0
0.01
2.5
0.01
2.5
0.04
1.0
0.08
1.0
0.13
1.5
0.21
2.5
0.16
2.5
0.16
1.5
0.04
2.5
0.79
6.5
0.16
1.0
1.36
1.0
1.36
2.5
0.79
1.0
0.47
Advertisement
Table of Contents
