National Semiconductor CP3BT26 User Manual page 44

Table 18 DMA Controller Registers
Name Address
ADCA2 FF F840h
ADRA2 FF F844h
ADCB2 FF F848h
ADRB2 FF F84Ch
BLTC2 FF F850h
BLTR2 FF F854h
DMACNTL2 FF F85Ch
DMASTAT2 FF F85Eh
ADCA3 FF F860h
ADRA3 FF F864h
ADCB3 FF F868h
ADRB3 FF F86Ch
BLTC3 FF F870h
BLTR3 FF F874h
DMACNTL3 FF F87Ch
DMASTAT3 FF F87Eh
9.6.1 Device A Address Counter Register (ADCAn)
The Device A Address Counter register is a 32-bit, read/
write register. It holds the current 24-bit address of either the
source data item or the destination location, depending on
the state of the DIR bit in the CNTLn register. The ADA bit
of DMACNTLn register controls whether to adjust the point-
er in the ADCAn register by the step size specified in the
INCA field of DMACNTLn register. The upper 8 bits of the
ADCAn register are reserved and always clear.
31 24 23
Reserved Device A Address Counter
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9.6.2
The Device A Address register is a 32-bit, read/write regis-
Description
ter. It holds the 24-bit starting address of either the next
source data block, or the next destination data area, according
Device A Address
to the DIR bit in the DMACNTLn register. The upper 8 bits of
Counter Register
the ADRAn register are reserved and always clear.
Device A Address
Register
Device B Address
Counter Register
Device B Address
9.6.3
Register
The Device B Address Counter register is a 32-bit, read/
Block Length
write register. It holds the current 24-bit address of either the
Counter Register
source data item, or the destination location, according to
the DIR bit in the CNTLn register. The ADCBn register is up-
Block Length Register
dated after each transfer cycle by INCB field of the
DMACNTLn register according to ADB bit of the
DMA Control Register
DMACNTLn register. In direct (flyby) mode, this register is
DMA Status Register
not used. The upper 8 bits of the ADCBn register are re-
served and always clear.
Device A Address
Counter Register
Device A Address
Register
Device B Address
Counter Register
9.6.4
The Device B Address register is a 32-bit, read/write regis-
Device B Address
ter. It holds the 24-bit starting address of either the next
Register
source data block or the next destination data area, accord-
Block Length
ing to the DIR bit in the CNTLn register. In direct (flyby)
Counter Register
mode, this register is not used. The upper 8 bits of the AD-
CRBn register are reserved and always clear.
Block Length Register
DMA Control Register
DMA Status Register
9.6.5
The Block Length Counter register is a 16-bit, read/write
register. It holds the current number of DMA transfers to be
executed in the current block. BLTCn is decremented by one
after each transfer cycle. A DMA transfer may consist of 1 or
2 bytes, as selected by the DMACNTLn.TCS bit.
0
Note: 0000h is interpreted as 2
44
Device A Address Register (ADRAn)
31 24 23
Reserved Device A Address
Device B Address Counter Register (ADCBn)
31 24 23
Reserved Device B Address Counter
Device B Address Register (ADRBn)
31 24 23
Reserved Device B Address
Block Length Counter Register (BLTCn)
15
Block Length Counter
0
0
0
0
16
-1 transfer cycles.