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Bus State
CLK
A[21:0]
A22 ('13 only)
SELx
(y ≠ x)
SELy
(y ≠ x)
D[15:0]
RD
WR[1:0]
Figure 132. Late Write Between Normal Read Cycles (No Wait States)
Normal Read
T1
T2
T1
t
4
t
5
t
5
t
, t
5
12
t
3
In
t
10
t
9
t
, t
6
13
265
Late Write
Normal Read
T2
T1
t
, t
, t
12
4
12
, t
t
, t
12
5
12
t
11
, t
12
t
, t
8
12
Out
t
, t
5
12
t
, t
6
13
T2
In
t
, t
5
12
DS125
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