National Semiconductor CP3BT26 User Manual page 234

Reprogrammable connectivity processor with bluetooth, usb, and can interfaces
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CAN
Memory
15
Registers
XI28
XI27
CMBn.ID1
ID10
CMBn.ID0
XI14 XI13 XI12 XI11 XI10
Data
Data
CMBn.DATA0
1.7
Data
Data
CMBn.DATA1
3.7
Data
Data
CMBn.DATA2
5.7
Data
Data
CMBn.DATA3
7.7
TSTP
TSTP
CMBn.TSTP
15
CMBn.CNTSTAT DLC3 DLC2 DLC1 DLC0
DMAC
20..16 15
Registers
ADCA
ADRA
ADCB
ADRB
BLTC
N/A
BLTR
N/A
DMACNTL
N/A
Res.
DMASTAT
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14
13
12
11
XI26
XI25
XI24
XI23
ID9
ID8
ID7
ID6
ID5
XI9
Data
Data
Data
Data
1.6
1.5
1.4
1.3
1.2
Data
Data
Data
Data
3.6
3.5
3.4
3.3
3.2
Data
Data
Data
Data
5.6
5.5
5.4
5.3
5.2
Data
Data
Data
Data
7.6
7.5
7.4
7.3
7.2
TSTP
TSTP
TSTP
TSTP
14
13
12
11
Reserved
14
13
12
11
INCB
ADB
INCA
N/A
10
9
8
7
XI22
XI21
XI20
XI19
ID4
ID3
ID2
ID1
XI8
XI7
XI6
XI5
Data
Data
Data
Data
1.1
1.0
2.7
2.6
Data
Data
Data
Data
3.1
3.0
4.7
4.6
Data
Data
Data
Data
5.1
5.0
6.7
6.6
Data
Data
Data
Data
7.1
7.0
8.7
8.6
TSTP
TSTP
TSTP
TSTP
10
9
8
7
PRI3 PRI2 PRI1 PRI0 ST3 ST2 ST1 ST0
10
9
8
7
Device A Address Counter
Device A Address
Device B Address Counter
Device B Address
Block Length Counter
Block Length
SW
ADA
Res. OT
RQ
234
6
5
4
3
2
XI18
SRR
IDE XI17 XI16 XI15
ID0
RTR
XI4
XI3
XI2
XI1
Data
Data
Data
Data
2.5
2.4
2.3
2.2
Data
Data
Data
Data
4.5
4.4
4.3
4.2
Data
Data
Data
Data
6.5
6.4
6.3
6.2
Data
Data
Data
Data
8.5
8.4
8.3
8.2
TSTP
TSTP
TSTP
TSTP
6
5
4
3
2
6
5
4
3
EO
DIR IND TCS
VR
CH
Reserved
VLD
AC
1
0
XI0
RTR
Data
Data
2.1
2.0
Data
Data
4.1
4.0
Data
Data
6.1
6.0
Data
Data
8.1
8.0
TSTP
TSTP
1
0
2
1
0
CH
ETC
EN
OVR TC

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