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14.1.6
Port High Drive Strength Register (PxHDRV)
The PxHDRV register is a byte-wide, read/write register that
controls the slew rate of the corresponding pins. The high
drive strength function is enabled when the corresponding
bits of the PxHDRV register are set. In both GPIO and alter-
nate function modes, the drive strength function is enabled
by the PxHDRV registers. At reset, the PxHDRV registers
are cleared, making the ports low speed.
7
PxHDRV
The PxHDRV bits control whether output pins
are driven with slow or fast slew rate.
–
0
Slow slew rate.
–
1
Fast slew rate.
14.1.7
Port Alternate Function Select Register
(PxALTS)
The PxALTS register selects which of two alternate func-
tions are selected for the port pin. These bits are ignored
unless the corresponding PxALT bits are set. Each port pin
can be controlled independently.
7
PxALTS
The PxALTS bits select among two alternate
functions. Table 30 shows the mapping of the
PxALTS bits to the alternate functions. Un-
used PxALTS bits must be clear.
Table 30 Alternate Function Select
Port Pin
PE0
PE1
PE2
PE3
PE4
PE5
PF0
PF1
PF2
PF3
PF4
PF5
PF6
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PxHDRV
PxALTS
PxALTS = 0
PxALTS = 1
UART0 RXD0
Reserved
UART0 TXD0
Reserved
UART0 RTS
Reserved
UART0 CTS
Reserved
UART0 CKX
TB
SRFS
NMI
MSK
TIO1
MDIDO
TIO2
MDODI
TIO3
MWCS
TIO4
SCK
TIO5
SFS
TIO6
STD
TIO7
Table 30 Alternate Function Select
Port Pin
PF7
PG0
PG1
PG2
0
PG3
PG4
PG5
PG6
PG7
PH0
PH1
PH2
PH3
PH4
0
PH5
PH6
PH7
PJ0
PJ1
PJ2
PJ3
PJ4
PJ5
PJ6
PJ7
70
PxALTS = 0
PxALTS = 1
SRD
TIO8
RFSYNC
Reserved
RFCE
Reserved
BTSEQ1
SRCLK
SCLK
Reserved
SDAT
Reserved
SLE
Reserved
WUI10
BTSEQ2
TA
BTSEQ3
UART1 RXD1
WUI11
UART1 TXD1
WUI12
UART2 RXD2
WUI13
UART2 TXD2
WUI14
UART3 RXD3
WUI15
UART3 TXD3
WUI16
CANRX
WUI17
CANTX
Reserved
WUI18
Reserved
WUI19
Reserved
WUI20
Reserved
WUI21
Reserved
WUI22
Reserved
WUI23
Reserved
WUI24
Reserved
ASYNC
WUI9
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