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CLC-CAPT-PCASM
Data Capture Board User's Guide
Section I. Introduction
The CLC3790093 Data Capture Board enables simple evaluation
of National Semiconductor's High Speed Analog to Digital Con-
verters (ADCs) and the Diversity Receiver Chip Set (DRCS). The
Data Capture Board interfaces the outputs of these devices to the
standard serial port available on the back of most Personal
Computers (PCs). We have provided PC software to control the
data capture function and Matlab
A block diagram of the evaluation test bed is shown below.
The Data Capture Board contains a field-programmable gate
array (FPGA) that controls its operation. An EPROM configures
the FPGA after power is applied. The serial interface is provided
by a UART (Universal Asynchronous Receiver/Transmitter), an
oscillator, and a level translator IC. The captured data is stored in
either three 32K x 8 static RAMs (organized into 24-bit words) or
in a FIFO containing 32K 18-bit words. LEDs provide a visual
indication of activity. DIP switches and a jumper configure several
capture functions.
Section II. Capturing Data from ADC
Evaluation Boards
Getting Started
To use the Data Capture board to capture data from a National
Semiconductor Analog to Digital converter, you will need the
following hardware, software, and documentation.
CLC5956
Evaluation Board
CLC5958
Evaluation Board
Digital Receiver
ChipSet (DRCS)
Evaluation Board
© 1999 National Semiconductor Corporation
Printed in the U.S.A.
®
scripts for data analysis.
National Semiconductor
High-Speed Converter
Evaluation Test Bed
Data
Capture
Board
Table of Contents
I. Introduction
II. Capturing Data from ADC
Evaluation Boards
III. Capturing Data from the DRCS
Evaluation Boards
IV. Data Analysis using Matlab
Script Files
May 1999
Rev 1.0.0
http://www.national.com
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Summary of Contents for National Semiconductor Data Capture Board CLC-CAPT-PCASM
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Page 1: Section I. Introduction
CLC-CAPT-PCASM Data Capture Board User’s Guide Section I. Introduction The CLC3790093 Data Capture Board enables simple evaluation of National Semiconductor’s High Speed Analog to Digital Con- verters (ADCs) and the Diversity Receiver Chip Set (DRCS). The Data Capture Board interfaces the outputs of these devices to the standard serial port available on the back of most Personal Computers (PCs). - Page 2 CLC5956 (12-bit 65MSPS ADC), or the CLC5958 (14-bit 52MSPS ADC). Each product has a unique evaluation board (CLC5956PCASM or CLC5958PCASM) which plugs into the data capture board. 3. Personal Computer. An IBM-Compatible PC running ® ® Windows 95, Windows...
- Page 3 complement number can be converted to offset binary by inverting the MSB. This is the first step in the Matlab routine for FFT analysis. CLC5956 Data Analog Input Condition Offset Binary Number Two's Complement Ain- >> Ain - Full Scale 0000 0000 0000 1000 0000 0000 Ain- >...
- Page 4 SMA Connectors The output clock SMA connector provides a signal that can be used to phase lock a signal source. The frequency is that of the input clock signal divided by 2. For example, with an attached CLC5958 ADC evaluation board at 52MSPS the clock output signal will be a 26MHz square wave.
- Page 5 Verify the connections and, if necessary, try the other COM port. (Note that you must have a clock applied to the ADC Evaluation board during this communication verification stage. Check to make sure that either an external clock or the TTL oscillator is installed, and that LED6 is on at reduced intensity.) Once you get a proper exit from this step, you are ready to configure the capture board.
- Page 6 To look at the data that you have just captured, left click on the “Plot_Data” button. If you have collected data with a 12-bit ADC at 52MSPS and a -2dBFS sinewave input at 5MHz, you will see two’s complement data that looks like this: Next, left click on the 12B_FFT button, and you will see the following FFT plot and performance summary.
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Page 7: Section Iii. Capturing Data From The Diversity Receiver Chipset (Drcs) Evaluation Board
(CLC-DRCS-PCASM) 3. DC Power Supply - The DRCS Evaluation and Capture Board combination require +5V at >1A. 4. An IBM-Compatible Personal Computer running Windows 95, Windows 98, or Windows NT with a serial port capable of 115,200 baud. 5. Serial data cable to connect the data capture board to the PC. - Page 8 24-bit words via the serial port as 96K bytes. Each word is interpreted as a 24-bit two’s complement integer and stored as 32K ASCII words in a user defined file. Each value is terminated with a carriage return (hexadecimal 0D). When a Diversity Receiver Evaluation Board is attached to the Data Capture Board, data narrower than 24 bits is aligned to the most significant bit with unused lower bits set to 0s.
- Page 9 The “Configure I/O” button opens the user port option menu window. Clicking the left mouse button selects the desired port (the default Windows address and IRQ is assumed). Clicking the “OK” button sends an identifica- tion command out the selected port and listens for the Capture board to echo back the command.
- Page 10 #4 & #5 as indicated in the Histogram Max Target table. Due to a high data resolution and relatively slow data rate, a relatively long period of time is required for generating histogram data from the DRCS with high decimation values in the DDC. Under some circumstances, the serial PC interface will time out.
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Page 11: Section Iv. Data Analysis Tools
** From the Windows Start Programs menu, launch the Capture program (it’s inside the C:\nsc folder). Right click inside the Control Panel and select Configure I/O and click the appropriate PC COM port button. Next, right click inside the Control Panel and select Configure Capture . - Page 12 ** DRCS_Serial “DRCS_ser_fft.m” intended for analysis of the DRCS 24-bit serial out- put data. Fsample is set to a default of 52e6/192 which is the GSM standard output rate of 270.833KS/s. The “search’ option is enabled; therefore, excluding the DC bins, the peak FFT bin is assumed to be the input fundamental.
- Page 13 CLC-CAPT-PCASM Evaluation Board - Layer 1 CLC-CAPT-PCASM Evaluation Board - Layer 2 CLC-CAPT-PCASM Evaluation Board - Layer 3 CLC-CAPT-PCASM Evaluation Board - Layer 4 http://www.national.com...
- Page 14 ! http://www.national.com (3). 74)3 FPGA1 )3*$ 208-pin TQFP EPF10K20 CLC-CAPT-PCASM Schematic Diagram...
- Page 15 Customer Design Applications Support National Semiconductor is committed to design excellence. For sales, literature and technical support, call the National Semiconductor Customer Response Group at 1-800-272-9959 or fax 1-800-737-7018. Life Support Policy National’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of National Semiconductor Corporation.