National Semiconductor CP3BT26 User Manual page 12

Reprogrammable connectivity processor with bluetooth, usb, and can interfaces
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Name
Pins
I/O
Input
X1CKI
1
Output
X1CKO
1
Input
X2CKI
1
Output
X2CKO
1
Input
RESET
1
I/O
ENV0
1
I/O
ENV1
1
ENV2
1
I/O
Input
TMS
1
Input
TCK
1
Input
TDI
1
Output
TDO
1
Output
RDY
1
Input
VCC
6
GND
6
Input
IOVCC
10
Input
IOGND
11
Input
AVCC
1
Input
1
Input
AGND
Input
ADVCC
1
1
Input
ADGND
1
I/O
RFDATA
1
I/O
SCL
1
I/O
SDA
I/O
D-
1
I/O
D+
1
Input
UVCC
1
1
Input
UGND
1
I/O
ADC0
1
I/O
ADC1
1
I/O
ADC2
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Table 3 CP3BT26 LQFP-144 Signal Descriptions
Primary Function
12 MHz Oscillator Input
12 MHz Oscillator Output
32 kHz Oscillator Input
32 kHz Oscillator Output
Chip general reset
Special mode select input with
internal pull-up during reset
Special mode select input with
internal pull-up during reset
Special mode select input with
internal pull-up during reset
JTAG Test Mode Select
(with internal weak pull-up)
JTAG Test Clock Input
(with internal weak pull-up)
JTAG Test Data Input
(with internal weak pull-up)
JTAG Test Data Output
NEXUS Ready Output
2.5V Core Logic
Power Supply
Core Ground
2.5
3.3V I/O Power Supply
I/O Ground
PLL Analog Power Supply
PLL Analog Ground
ADC Analog Power Supply
ADC Analog Ground
Bluetooth RX/TX Data Pin
ACCESS.bus Clock
ACCESS.bus Serial Data
USB D- Upstream Port
USB D+ Upstream Port
3.3V USB Transceiver Supply
USB Transceiver Ground
ADC Input Channel 0
ADC Input Channel 1
ADC Input Channel 2
Alternate
Name
BBCLK
BB reference clock for the RF Interface
None
None
None
None
None
None
None
None
PLLCLK
PLL Clock Output
CPUCLK
CPU Clock Output
SLOWCLK
Slow Clock Output
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
TSX+
Touchscreen X+ contact
TSY+
Touchscreen Y+ contact
TSX-
Touchscreen X- contact
12
Alternate Function

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