National Semiconductor CP3BT26 User Manual page 248

RESET
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X1CKI
t
X1h
X2CKI
t
X2h
Figure 110. Clock Timing
CLK
t
lS
t
IW
NMI
Figure 111. NMI Signal Timing
CLK
Figure 112. Non-Power-On Reset
0.9 VCC
VCC
0.1 VCC
Figure 113. Power-On Reset
t
X1p
t
X1l
t
X2p
t
X2l
t
lH
t
RST
t
R
DS115
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DS095
DS096
DS097