National Semiconductor CP3BT26 User Manual page 75

SDAT
H2 H1 H0 W
SCLK
SLE
SDAT
H2 H1 H0 R
SCLK
SLE
An example of a 32-bit write is shown in Table 31. In this ex-
ample, the 32-bit value FFFF DC04h is written to register
address 0Ah. In cycle 1, the high word (FFFFh) is written. In
the first part of cycle 2, the CP3BT26 drives the header, R/
W bit, and register address for a read cycle. In the second
part of cycle 2, the LMX5252 drives the counter value. The
Cycle Serial Data on SDAT
1 101 0 01010 1111111111111111
101 1 01010
2
0000000000000000
3 101 0 01010 1101110000000100
101 1 01010
4
0000000000000001
A4 A3 A2 A1 A0 D31 D30 D16
Figure 18. 32-Bit Write Timing
A4 A3 A2 A1 A0 D31 D16
Figure 19. 32-Bit Read Timing
Table 31 Example of 32-Bit Write with Interleaved Reads
Write cycle driven by CP3BT26. Data is FFFFh. Address is 0Ah.
First part of read cycle driven by CP3BT26. Address is 0Ah.
Second part of read cycle driven by LMX5252. Counter value is 0.
Write cycle driven by CP3BT26. Data is DC04h. Address is 0Ah.
First part of read cycle driven by CP3BT26. Address is 0Ah.
Second part of read cycle driven by LMX5252. Counter value is 1.
H2 H1 H0 W A4 A3
>500 ns
H2 H1 H0 R A4 A3
>500 ns
counter value is 0, which indicates one word has been writ-
ten. In cycle 3, the low word (DC04h) is written. In the first
part of cycle 4, the CP3BT26 drives the header, R/W bit,
and register address for a read cycle. In the second part of
cycle 4, the LMX5252 drives the counter value. The counter
value is 1, which indicates two words have been written.
Description
75
A2 A1 A0 D15 D14 D0
DS322
A2 A1 A0 D15 D0
DS323
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